.asic_reset = &r100_asic_reset,
        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
        .gart_set_page = &r100_pci_gart_set_page,
-       .ring_start = &r100_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r100_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r100_cs_parse,
+                       .ring_start = &r100_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &r100_asic_reset,
        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
        .gart_set_page = &r100_pci_gart_set_page,
-       .ring_start = &r100_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r100_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r100_cs_parse,
+                       .ring_start = &r100_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
        .gart_set_page = &r100_pci_gart_set_page,
-       .ring_start = &r300_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r300_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r300_cs_parse,
+                       .ring_start = &r300_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
        .gart_set_page = &rv370_pcie_gart_set_page,
-       .ring_start = &r300_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r300_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r300_cs_parse,
+                       .ring_start = &r300_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
        .gart_set_page = &rv370_pcie_gart_set_page,
-       .ring_start = &r300_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r300_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r300_cs_parse,
+                       .ring_start = &r300_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &rs400_gart_tlb_flush,
        .gart_set_page = &rs400_gart_set_page,
-       .ring_start = &r300_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r300_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r300_cs_parse,
+                       .ring_start = &r300_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &rs600_asic_reset,
        .gart_tlb_flush = &rs600_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
-       .ring_start = &r300_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r300_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r300_cs_parse,
+                       .ring_start = &r300_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &rs600_asic_reset,
        .gart_tlb_flush = &rs400_gart_tlb_flush,
        .gart_set_page = &rs400_gart_set_page,
-       .ring_start = &r300_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r300_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r300_cs_parse,
+                       .ring_start = &r300_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &rs600_asic_reset,
        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
        .gart_set_page = &rv370_pcie_gart_set_page,
-       .ring_start = &rv515_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r300_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r300_cs_parse,
+                       .ring_start = &rv515_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &rs600_asic_reset,
        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
        .gart_set_page = &rv370_pcie_gart_set_page,
-       .ring_start = &rv515_ring_start,
-       .ring_test = &r100_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r100_ring_ib_execute,
                        .emit_fence = &r300_fence_ring_emit,
                        .emit_semaphore = &r100_semaphore_ring_emit,
                        .cs_parse = &r300_cs_parse,
+                       .ring_start = &rv515_ring_start,
+                       .ring_test = &r100_ring_test,
+                       .ib_test = &r100_ib_test,
                }
        },
        .irq = {
        .asic_reset = &r600_asic_reset,
        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
-       .ring_test = &r600_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r600_ring_ib_execute,
                        .emit_fence = &r600_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                        .cs_parse = &r600_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
                }
        },
        .irq = {
        .asic_reset = &r600_asic_reset,
        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
-       .ring_test = &r600_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r600_ring_ib_execute,
                        .emit_fence = &r600_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                        .cs_parse = &r600_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
                }
        },
        .irq = {
        .vga_set_state = &r600_vga_set_state,
        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
-       .ring_test = &r600_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &r600_ring_ib_execute,
                        .emit_fence = &r600_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                        .cs_parse = &r600_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
                }
        },
        .irq = {
        .vga_set_state = &r600_vga_set_state,
        .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
-       .ring_test = &r600_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &evergreen_ring_ib_execute,
                        .emit_fence = &r600_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                        .cs_parse = &evergreen_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
                }
        },
        .irq = {
        .vga_set_state = &r600_vga_set_state,
        .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
-       .ring_test = &r600_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &evergreen_ring_ib_execute,
                        .emit_fence = &r600_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                        .cs_parse = &evergreen_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
                },
        },
        .irq = {
        .vga_set_state = &r600_vga_set_state,
        .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
-       .ring_test = &r600_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &evergreen_ring_ib_execute,
                        .emit_fence = &r600_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                        .cs_parse = &evergreen_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
                }
        },
        .irq = {
        .vga_set_state = &r600_vga_set_state,
        .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
-       .ring_test = &r600_ring_test,
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &cayman_ring_ib_execute,
                        .emit_fence = &cayman_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                        .cs_parse = &evergreen_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
                },
                [CAYMAN_RING_TYPE_CP1_INDEX] = {
                        .ib_execute = &cayman_ring_ib_execute,
                        .emit_fence = &cayman_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                        .cs_parse = &evergreen_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
                },
                [CAYMAN_RING_TYPE_CP2_INDEX] = {
                        .ib_execute = &cayman_ring_ib_execute,
                        .emit_fence = &cayman_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                        .cs_parse = &evergreen_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
                }
        },
        .irq = {