phy: phy-rockchip-samsung-hdptx: Supplement some register names with their full version

Complete the register names of CMN_REG(0081) and CMN_REG(0087) to their
full version, and it can help to better match the datasheet.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250205105157.580060-3-damon.ding@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index dfcc37b1c8a6db4cef86090960156bad192dfc44..77b817ac90599973f51f0f4f964e7eb1eded79fb 100644 (file)
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -82,14 +82,14 @@
 #define ROPLL_SSC_EN                   BIT(0)
 /* CMN_REG(0081) */
 #define OVRD_PLL_CD_CLK_EN             BIT(8)
-#define PLL_CD_HSCLK_EAST_EN           BIT(0)
+#define ANA_PLL_CD_HSCLK_EAST_EN       BIT(0)
 /* CMN_REG(0086) */
 #define PLL_PCG_POSTDIV_SEL_MASK       GENMASK(7, 4)
 #define PLL_PCG_CLK_SEL_MASK           GENMASK(3, 1)
 #define PLL_PCG_CLK_EN                 BIT(0)
 /* CMN_REG(0087) */
-#define PLL_FRL_MODE_EN                        BIT(3)
-#define PLL_TX_HS_CLK_EN               BIT(2)
+#define ANA_PLL_FRL_MODE_EN            BIT(3)
+#define ANA_PLL_TX_HS_CLK_EN           BIT(2)
 /* CMN_REG(0089) */
 #define LCPLL_ALONE_MODE               BIT(1)
 /* CMN_REG(0097) */