drm/amd/display: disable display fresh from MALL on an edge case for DCN321

[Why&How]
When using a 4k monitor when cursor caching is not supported due to
framebuffer being on an uncacheable address, enabling display refresh
from MALL would trigger corruption if SS is enabled.

Prevent entering SS if we are on the edge case and cursor caching is not
possible. Do this only if cursor size larger than a 64x64@4bpp. Pull the
cursor size calculation out of if condition since cursor address may not
be set on all platforms

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 4e965a0c2484448fe1837058cf9f87f8317b25bb..a54cb79e7ba08e8f0d6ceee02b6d5caffeb9739e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -295,23 +295,24 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *c
                }
 
                // Include cursor size for CAB allocation
+               cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
+               switch (stream->cursor_attributes.color_format) {
+               case CURSOR_MODE_MONO:
+                       cursor_size /= 2;
+                       break;
+               case CURSOR_MODE_COLOR_1BIT_AND:
+               case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
+               case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
+                       cursor_size *= 4;
+                       break;
+
+               case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
+               case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
+                       cursor_size *= 8;
+                       break;
+               }
+
                if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) {
-                       cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
-                       switch (stream->cursor_attributes.color_format) {
-                       case CURSOR_MODE_MONO:
-                               cursor_size /= 2;
-                               break;
-                       case CURSOR_MODE_COLOR_1BIT_AND:
-                       case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
-                       case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
-                               cursor_size *= 4;
-                               break;
-
-                       case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
-                       case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
-                               cursor_size *= 8;
-                               break;
-                       }
                        cache_lines_used += dcn32_cache_lines_for_surface(dc, cursor_size,
                                        plane->address.grph.cursor_cache_addr.quad_part);
                }
@@ -325,6 +326,16 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *c
        if (cache_lines_used % lines_per_way > 0)
                num_ways++;
 
+       if (stream->cursor_position.enable &&
+           !plane->address.grph.cursor_cache_addr.quad_part &&
+           cursor_size > 16384)
+               /* Cursor caching is not supported since it won't be on the same line.
+                * So we need an extra line to accommodate it. With large cursors and a single 4k monitor
+                * this case triggers corruption. If we're at the edge, then dont trigger display refresh
+                * from MALL. We only need to cache cursor if its greater that 64x64 at 4 bpp.
+                */
+               num_ways++;
+
        return num_ways;
 }