/* CCGR5 */
        clks[IMX6UL_CLK_ROM]            = imx_clk_gate2("rom",          "ahb",          base + 0x7c,    0);
        clks[IMX6UL_CLK_SDMA]           = imx_clk_gate2("sdma",         "ahb",          base + 0x7c,    6);
+       clks[IMX6UL_CLK_KPP]            = imx_clk_gate2("kpp",          "ipg",          base + 0x7c,    8);
        clks[IMX6UL_CLK_WDOG2]          = imx_clk_gate2("wdog2",        "ipg",          base + 0x7c,    10);
        clks[IMX6UL_CLK_SPBA]           = imx_clk_gate2("spba",         "ipg",          base + 0x7c,    12);
        clks[IMX6UL_CLK_SPDIF]          = imx_clk_gate2_shared("spdif",         "spdif_podf",   base + 0x7c,    14, &share_count_audio);
 
 #define IMX6UL_CLK_CSI_SEL             221
 #define IMX6UL_CLK_CSI_PODF            222
 #define IMX6UL_CLK_PLL3_120M           223
+#define IMX6UL_CLK_KPP                 224
 
-#define IMX6UL_CLK_END                 224
+#define IMX6UL_CLK_END                 225
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */