TSE PCS SGMII ethernet has an issue where switching speed doesn't work
caused by a faulty register macro offset. This fixes the issue.
Signed-off-by: Jia Jie Ho <ho.jia.jie@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
 #define TSE_PCS_SGMII_LINK_TIMER_0                     0x0D40
 #define TSE_PCS_SGMII_LINK_TIMER_1                     0x0003
 #define TSE_PCS_SW_RESET_TIMEOUT                       100
-#define TSE_PCS_USE_SGMII_AN_MASK                      BIT(2)
-#define TSE_PCS_USE_SGMII_ENA                          BIT(1)
+#define TSE_PCS_USE_SGMII_AN_MASK                      BIT(1)
+#define TSE_PCS_USE_SGMII_ENA                          BIT(0)
 
 #define SGMII_ADAPTER_CTRL_REG                         0x00
 #define SGMII_ADAPTER_DISABLE                          0x0001