powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush

For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will invalidate all
related caches (radix__tlb_flush()). Hence the pwc flush is not needed.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 83dc1ccc2fa1a2840e79c221e85368aaf06a41fb..f3e58bd60d1a2e6097432ee9467f30071b6524ea 100644 (file)
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -129,6 +129,12 @@ void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 {
        unsigned long pid;
        struct mm_struct *mm = tlb->mm;
+       /*
+        * If we are doing a full mm flush, we will do a tlb flush
+        * with RIC_FLUSH_ALL later.
+        */
+       if (tlb->fullmm)
+               return;
 
        preempt_disable();
 
@@ -195,6 +201,12 @@ void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
        unsigned long pid;
        struct mm_struct *mm = tlb->mm;
 
+       /*
+        * If we are doing a full mm flush, we will do a tlb flush
+        * with RIC_FLUSH_ALL later.
+        */
+       if (tlb->fullmm)
+               return;
        preempt_disable();
 
        pid = mm->context.id;