drm/i915: move the edram detection out of uncore init

edram is not part of uncore and there is no requirement for the
detection to be done before we initialize the uncore functions. The
first check on HAS_EDRAM is in the ggtt_init path, so move it to
i915_driver_init_hw, where other dram-related detection happens.

While at it, save the size in MB instead of the capabilities because the
size is the only thing we look at outside of the init function.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190328174533.31532-1-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index bb2c16c439ea6eafc6cbc0f3e6597fa8301d0cb9..84c0c2a50f7838ee6f8fcb3d81f669d7f01a8288 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2087,8 +2087,8 @@ static int i915_llc(struct seq_file *m, void *data)
        const bool edram = INTEL_GEN(dev_priv) > 8;
 
        seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
-       seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
-                  intel_uncore_edram_size(dev_priv)/1024/1024);
+       seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
+                  dev_priv->edram_size_mb);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bbe1a5d56480b52a396a7b3160e91cac332e2016..4d5f3f2d94eefe7096c717b1f480e256867b41fc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1441,6 +1441,45 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
                      dram_info->ranks, yesno(dram_info->is_16gb_dimm));
 }
 
+static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
+{
+       const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
+       const unsigned int sets[4] = { 1, 1, 2, 2 };
+
+       return EDRAM_NUM_BANKS(cap) *
+               ways[EDRAM_WAYS_IDX(cap)] *
+               sets[EDRAM_SETS_IDX(cap)];
+}
+
+static void edram_detect(struct drm_i915_private *dev_priv)
+{
+       u32 edram_cap = 0;
+
+       if (!(IS_HASWELL(dev_priv) ||
+             IS_BROADWELL(dev_priv) ||
+             INTEL_GEN(dev_priv) >= 9))
+               return;
+
+       edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
+
+       /* NB: We can't write IDICR yet because we don't have gt funcs set up */
+
+       if (!(edram_cap & EDRAM_ENABLED))
+               return;
+
+       /*
+        * The needed capability bits for size calculation are not there with
+        * pre gen9 so return 128MB always.
+        */
+       if (INTEL_GEN(dev_priv) < 9)
+               dev_priv->edram_size_mb = 128;
+       else
+               dev_priv->edram_size_mb =
+                       gen9_edram_size_mb(dev_priv, edram_cap);
+
+       DRM_INFO("Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
+}
+
 /**
  * i915_driver_init_hw - setup state requiring device access
  * @dev_priv: device private
@@ -1483,6 +1522,9 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
        intel_sanitize_options(dev_priv);
 
+       /* needs to be done before ggtt probe */
+       edram_detect(dev_priv);
+
        i915_perf_init(dev_priv);
 
        ret = i915_ggtt_probe_hw(dev_priv);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a32bfc7ec5ea13cc2a403c0558a99ee345acdde6..f75600fa77c600f867c26f9c7fda13fbe179ad7a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1707,8 +1707,11 @@ struct drm_i915_private {
 
        struct intel_l3_parity l3_parity;
 
-       /* Cannot be determined by PCIID. You must always read a register. */
-       u32 edram_cap;
+       /*
+        * edram size in MB.
+        * Cannot be determined by PCIID. You must always read a register.
+        */
+       u32 edram_size_mb;
 
        /*
         * Protects RPS/RC6 register access and PCU communication.
@@ -2468,7 +2471,7 @@ static inline unsigned int i915_sg_segment_size(void)
 
 #define HAS_LLC(dev_priv)      (INTEL_INFO(dev_priv)->has_llc)
 #define HAS_SNOOP(dev_priv)    (INTEL_INFO(dev_priv)->has_snoop)
-#define HAS_EDRAM(dev_priv)    (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
+#define HAS_EDRAM(dev_priv)    ((dev_priv)->edram_size_mb)
 #define HAS_WT(dev_priv)       ((IS_HASWELL(dev_priv) || \
                                 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
 

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 5c80704bf283dcba425d0e6c1d78ae705c98c818..106df24f20a501f838502df9172eb4dbd8492925 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -420,51 +420,6 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
        return fw; /* track the lost user forcewake domains */
 }
 
-static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
-{
-       const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
-       const unsigned int sets[4] = { 1, 1, 2, 2 };
-       const u32 cap = dev_priv->edram_cap;
-
-       return EDRAM_NUM_BANKS(cap) *
-               ways[EDRAM_WAYS_IDX(cap)] *
-               sets[EDRAM_SETS_IDX(cap)] *
-               1024 * 1024;
-}
-
-u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
-{
-       if (!HAS_EDRAM(dev_priv))
-               return 0;
-
-       /* The needed capability bits for size calculation
-        * are not there with pre gen9 so return 128MB always.
-        */
-       if (INTEL_GEN(dev_priv) < 9)
-               return 128 * 1024 * 1024;
-
-       return gen9_edram_size(dev_priv);
-}
-
-static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
-{
-       if (IS_HASWELL(dev_priv) ||
-           IS_BROADWELL(dev_priv) ||
-           INTEL_GEN(dev_priv) >= 9) {
-               dev_priv->edram_cap = __raw_uncore_read32(&dev_priv->uncore,
-                                                         HSW_EDRAM_CAP);
-
-               /* NB: We can't write IDICR yet because we do not have gt funcs
-                * set up */
-       } else {
-               dev_priv->edram_cap = 0;
-       }
-
-       if (HAS_EDRAM(dev_priv))
-               DRM_INFO("Found %lluMB of eDRAM\n",
-                        intel_uncore_edram_size(dev_priv) / (1024 * 1024));
-}
-
 static bool
 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 {
@@ -1584,7 +1539,6 @@ int intel_uncore_init(struct intel_uncore *uncore)
        if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
                uncore->flags |= UNCORE_HAS_FORCEWAKE;
 
-       intel_uncore_edram_detect(i915);
        intel_uncore_fw_domains_init(uncore);
        __intel_uncore_early_sanitize(uncore, 0);
 

diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 50d226f687538052914fae5b1f0407f30e2a9f76..896585a1c2dd6ac7f9ed8df1de243ef58c0b5294 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -187,7 +187,6 @@ void intel_uncore_suspend(struct intel_uncore *uncore);
 void intel_uncore_resume_early(struct intel_uncore *uncore);
 void intel_uncore_runtime_resume(struct intel_uncore *uncore);
 
-u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
 void assert_forcewakes_inactive(struct intel_uncore *uncore);
 void assert_forcewakes_active(struct intel_uncore *uncore,
                              enum forcewake_domains fw_domains);