arm64: dts: mediatek: mt7988: Add t-phy for ssusb1

USB controller needs phys for working properly.
On mt7988 ssusb0 uses a xs-phy, ssusb uses t-phy.
For now add the t-phy for ssusb1. We can reuse the mt7986 compatible
here.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-10-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index f8b01f3fff3279b9ba6f1ed0bb786ffa422bd04a..209d170bce7f694ce6f4b4c731974b4e4fbc77f3 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -349,6 +349,8 @@
                                 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
                                 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
                        clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+                       phys = <&tphyu2port0 PHY_TYPE_USB2>,
+                              <&tphyu3port0 PHY_TYPE_USB3>;
                        status = "disabled";
                };
 
@@ -371,6 +373,29 @@
                        status = "disabled";
                };
 
+               t-phy@11c50000 {
+                       compatible = "mediatek,mt7986-tphy",
+                                    "mediatek,generic-tphy-v2";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       status = "disabled";
+
+                       tphyu2port0: usb-phy@11c50000 {
+                               reg = <0 0x11c50000 0 0x700>;
+                               clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                       };
+
+                       tphyu3port0: usb-phy@11c50700 {
+                               reg = <0 0x11c50700 0 0x900>;
+                               clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                       };
+               };
+
                clock-controller@11f40000 {
                        compatible = "mediatek,mt7988-xfi-pll";
                        reg = <0 0x11f40000 0 0x1000>;