net: pcs: xpcs: use FIELD_PREP() and FIELD_GET()

Convert xpcs to use the bitfield macros rather than definining the
bitfield shifts and open-coding the insertion and extraction of these
bitfields.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
index 805856cabba147feeb2b08cb05596a4ebabba48a..f55bc180c6249b46b6cb3763a53925e2b395ba39 100644 (file)
--- a/drivers/net/pcs/pcs-xpcs.c
+++ b/drivers/net/pcs/pcs-xpcs.c
@@ -592,7 +592,8 @@ int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
                ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
                      DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
                      DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
-                     mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT;
+                     FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS,
+                                mult_fact_100ns);
        } else {
                ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
                       DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
@@ -681,9 +682,8 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
                return ret;
 
        ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
-       ret |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
-               DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
-               DW_VR_MII_PCS_MODE_MASK);
+       ret |= FIELD_PREP(DW_VR_MII_PCS_MODE_MASK,
+                         DW_VR_MII_PCS_MODE_C37_SGMII);
        if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
                ret |= DW_VR_MII_AN_CTRL_8BIT;
                /* Hardware requires it to be PHY side SGMII */
@@ -691,8 +691,7 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
        } else {
                tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII;
        }
-       ret |= tx_conf << DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
-               DW_VR_MII_TX_CONFIG_MASK;
+       ret |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf);
        ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
        if (ret < 0)
                return ret;
@@ -971,8 +970,7 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
 
                state->link = true;
 
-               speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >>
-                             DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT;
+               speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret);
                if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
                        state->speed = SPEED_1000;
                else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)

diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h
index 1b546eae8280c67aff8c59512a74e2c7f3ec5f46..8902485730a23dc1cc2ef3c0c4829581c765a3e8 100644 (file)
--- a/drivers/net/pcs/pcs-xpcs.h
+++ b/drivers/net/pcs/pcs-xpcs.h
@@ -77,11 +77,9 @@
 
 /* VR_MII_AN_CTRL */
 #define DW_VR_MII_AN_CTRL_8BIT                 BIT(8)
-#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT      3
 #define DW_VR_MII_TX_CONFIG_MASK               BIT(3)
 #define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII     0x1
 #define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII     0x0
-#define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT       1
 #define DW_VR_MII_PCS_MODE_MASK                        GENMASK(2, 1)
 #define DW_VR_MII_PCS_MODE_C37_1000BASEX       0x0
 #define DW_VR_MII_PCS_MODE_C37_SGMII           0x2
@@ -90,7 +88,6 @@
 /* VR_MII_AN_INTR_STS */
 #define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR      BIT(0)
 #define DW_VR_MII_AN_STS_C37_ANSGM_FD          BIT(1)
-#define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT    2
 #define DW_VR_MII_AN_STS_C37_ANSGM_SP          GENMASK(3, 2)
 #define DW_VR_MII_C37_ANSGM_SP_10              0x0
 #define DW_VR_MII_C37_ANSGM_SP_100             0x1
@@ -114,7 +111,6 @@
 #define DW_VR_MII_EEE_TX_EN_CTRL               BIT(4)  /* Tx Control Enable */
 #define DW_VR_MII_EEE_RX_EN_CTRL               BIT(7)  /* Rx Control Enable */
 
-#define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT    8
 #define DW_VR_MII_EEE_MULT_FACT_100NS          GENMASK(11, 8)
 
 /* VR MII EEE Control 1 defines */