drm/amdgpu: only use one gfx pipe for Sienna_Cichlid

Only enable one gfx pipe for sienna_cichlid currently.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f0955b3257980ef47f906482f4aaa316e327ac32..cc1835cd0c9168316ff49666d46faeb2ca93eed2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -55,7 +55,7 @@
  * 2. Async ring
  */
 #define GFX10_NUM_GFX_RINGS_NV1X       1
-#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid     2
+#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid     1
 #define GFX10_MEC_HPD_SIZE     2048
 
 #define F32_CE_PROGRAM_RAM_SIZE                65536
@@ -4232,7 +4232,7 @@ static int gfx_v10_0_sw_init(void *handle)
                break;
        case CHIP_SIENNA_CICHLID:
                adev->gfx.me.num_me = 1;
-               adev->gfx.me.num_pipe_per_me = 2;
+               adev->gfx.me.num_pipe_per_me = 1;
                adev->gfx.me.num_queue_per_pipe = 1;
                adev->gfx.mec.num_mec = 2;
                adev->gfx.mec.num_pipe_per_mec = 4;