static u32 next_vm_id = 0;
 static bool next_vm_id_wrapped = 0;
 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
-enum avic_modes avic_mode;
+bool x2avic_enabled;
 
 /*
  * This is a wrapper of struct amd_iommu_ir_data.
         * (deletes the memslot) if any vCPU has x2APIC enabled, thus enabling
         * AVIC in hybrid mode activates only the doorbell mechanism.
         */
-       if (apic_x2apic_mode(svm->vcpu.arch.apic) &&
-           avic_mode == AVIC_MODE_X2) {
+       if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) {
                vmcb->control.int_ctl |= X2APIC_MODE_MASK;
                vmcb->control.avic_physical_id |= X2AVIC_MAX_PHYSICAL_ID;
                /* Disabling MSR intercept for x2APIC registers */
        u64 *avic_physical_id_table;
        struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
 
-       if ((avic_mode == AVIC_MODE_X1 && index > AVIC_MAX_PHYSICAL_ID) ||
-           (avic_mode == AVIC_MODE_X2 && index > X2AVIC_MAX_PHYSICAL_ID))
+       if ((!x2avic_enabled && index > AVIC_MAX_PHYSICAL_ID) ||
+           (index > X2AVIC_MAX_PHYSICAL_ID))
                return NULL;
 
        avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
        int id = vcpu->vcpu_id;
        struct vcpu_svm *svm = to_svm(vcpu);
 
-       if ((avic_mode == AVIC_MODE_X1 && id > AVIC_MAX_PHYSICAL_ID) ||
-           (avic_mode == AVIC_MODE_X2 && id > X2AVIC_MAX_PHYSICAL_ID))
+       if ((!x2avic_enabled && id > AVIC_MAX_PHYSICAL_ID) ||
+           (id > X2AVIC_MAX_PHYSICAL_ID))
                return -EINVAL;
 
        if (!vcpu->arch.apic->regs)
        struct vcpu_svm *svm = to_svm(vcpu);
        struct vmcb *vmcb = svm->vmcb01.ptr;
 
-       if (!lapic_in_kernel(vcpu) || avic_mode == AVIC_MODE_NONE)
-               return;
-
-       if (!enable_apicv)
+       if (!lapic_in_kernel(vcpu) || !enable_apicv)
                return;
 
        if (kvm_vcpu_apicv_active(vcpu)) {
        if (!npt_enabled)
                return false;
 
+       /* AVIC is a prerequisite for x2AVIC. */
+       if (!boot_cpu_has(X86_FEATURE_AVIC) && !force_avic) {
+               if (boot_cpu_has(X86_FEATURE_X2AVIC)) {
+                       pr_warn(FW_BUG "Cannot support x2AVIC due to AVIC is disabled");
+                       pr_warn(FW_BUG "Try enable AVIC using force_avic option");
+               }
+               return false;
+       }
+
        if (boot_cpu_has(X86_FEATURE_AVIC)) {
-               avic_mode = AVIC_MODE_X1;
                pr_info("AVIC enabled\n");
        } else if (force_avic) {
                /*
                 * Some older systems does not advertise AVIC support.
                 * See Revision Guide for specific AMD processor for more detail.
                 */
-               avic_mode = AVIC_MODE_X1;
                pr_warn("AVIC is not supported in CPUID but force enabled");
                pr_warn("Your system might crash and burn");
        }
 
        /* AVIC is a prerequisite for x2AVIC. */
-       if (boot_cpu_has(X86_FEATURE_X2AVIC)) {
-               if (avic_mode == AVIC_MODE_X1) {
-                       avic_mode = AVIC_MODE_X2;
-                       pr_info("x2AVIC enabled\n");
-               } else {
-                       pr_warn(FW_BUG "Cannot support x2AVIC due to AVIC is disabled");
-                       pr_warn(FW_BUG "Try enable AVIC using force_avic option");
-               }
-       }
+       x2avic_enabled = boot_cpu_has(X86_FEATURE_X2AVIC);
+       if (x2avic_enabled)
+               pr_info("x2AVIC enabled\n");
 
-       if (avic_mode != AVIC_MODE_NONE)
-               amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
+       amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
 
-       return !!avic_mode;
+       return true;
 }