LoongArch: Add architectural preparation for CPUFreq

Add architectural preparation for CPUFreq driver, including: Kconfig,
register definition and platform device registration.

Some of LoongArch processors support DVFS, their IOCSR.FEATURES has
IOCSRF_FREQSCALE set. And they has a micro-core in the package called
SMC (System Management Controller) to scale frequency, voltage, etc.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 0693b621ebd4b56db8744a6d83c80b96ad7a1424..9687b1d241269f37cb66a20d0624792bfb5bd006 100644 (file)
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -702,6 +702,7 @@ config ARCH_HIBERNATION_POSSIBLE
 
 source "kernel/power/Kconfig"
 source "drivers/acpi/Kconfig"
+source "drivers/cpufreq/Kconfig"
 
 endmenu
 

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index c430df59537654c699f36e2d19d96e6e216d2d61..1501f0f8b06ee59db0a596273452e2208fce7656 100644 (file)
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1061,11 +1061,14 @@
 #define LOONGARCH_IOCSR_NODECNT                0x408
 
 #define LOONGARCH_IOCSR_MISC_FUNC      0x420
+#define  IOCSR_MISC_FUNC_SOFT_INT      BIT_ULL(10)
 #define  IOCSR_MISC_FUNC_TIMER_RESET   BIT_ULL(21)
 #define  IOCSR_MISC_FUNC_EXT_IOI_EN    BIT_ULL(48)
 
 #define LOONGARCH_IOCSR_CPUTEMP                0x428
 
+#define LOONGARCH_IOCSR_SMCMBX         0x51c
+
 /* PerCore CSR, only accessible by local cores */
 #define LOONGARCH_IOCSR_IPI_STATUS     0x1000
 #define LOONGARCH_IOCSR_IPI_EN         0x1004

diff --git a/arch/loongarch/power/platform.c b/arch/loongarch/power/platform.c
index 3ea8e07aa225f959ad54138a8079bb6a4648eb33..a19353f7d1b071212ab7ded9cc81edd07617b955 100644 (file)
--- a/arch/loongarch/power/platform.c
+++ b/arch/loongarch/power/platform.c
@@ -34,6 +34,21 @@ void enable_pci_wakeup(void)
                acpi_write_bit_register(ACPI_BITREG_PCIEXP_WAKE_DISABLE, 0);
 }
 
+static struct platform_device loongson3_cpufreq_device = {
+       .name = "loongson3_cpufreq",
+       .id = -1,
+};
+
+static int __init loongson_cpufreq_init(void)
+{
+       if (!cpu_has_scalefreq)
+               return -ENODEV;
+
+       return platform_device_register(&loongson3_cpufreq_device);
+}
+
+arch_initcall(loongson_cpufreq_init);
+
 static int __init loongson3_acpi_suspend_init(void)
 {
 #ifdef CONFIG_ACPI