ap4evb WVGA LCDC panel expect 33.3MHz for dot-clock,
but current dot-clock was 50.0MHz.
This patch modify clock divider value.
Signed-off-by: Makoto Ueda <makoto.ueda.ub@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
 
        lcdc_info.clock_source                  = LCDC_CLK_BUS;
        lcdc_info.ch[0].interface_type          = RGB18;
-       lcdc_info.ch[0].clock_divider           = 2;
+       lcdc_info.ch[0].clock_divider           = 3;
        lcdc_info.ch[0].flags                   = 0;
        lcdc_info.ch[0].lcd_size_cfg.width      = 152;
        lcdc_info.ch[0].lcd_size_cfg.height     = 91;