drm/amd/display: add DPP and MPC color caps to DTN log

Add color caps information for DPP and MPC block to show HW color caps.

Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 2ab5dfcc326d283f283d326f18d0fae54054bd44..d923d8d915f92df65849801aca5f406181555909 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -347,6 +347,24 @@ static void dcn10_log_color_state(struct dc *dc,
                DTN_INFO("\n");
        }
        DTN_INFO("\n");
+       DTN_INFO("DPP Color Caps: input_lut_shared:%d  icsc:%d"
+                "  dgam_ram:%d  dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d"
+                "  post_csc:%d  gamcor:%d  dgam_rom_for_yuv:%d  3d_lut:%d"
+                "  blnd_lut:%d  oscs:%d\n\n",
+                dc->caps.color.dpp.input_lut_shared,
+                dc->caps.color.dpp.icsc,
+                dc->caps.color.dpp.dgam_ram,
+                dc->caps.color.dpp.dgam_rom_caps.srgb,
+                dc->caps.color.dpp.dgam_rom_caps.bt2020,
+                dc->caps.color.dpp.dgam_rom_caps.gamma2_2,
+                dc->caps.color.dpp.dgam_rom_caps.pq,
+                dc->caps.color.dpp.dgam_rom_caps.hlg,
+                dc->caps.color.dpp.post_csc,
+                dc->caps.color.dpp.gamma_corr,
+                dc->caps.color.dpp.dgam_rom_for_yuv,
+                dc->caps.color.dpp.hw_3d_lut,
+                dc->caps.color.dpp.ogam_ram,
+                dc->caps.color.dpp.ocsc);
 
        DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
        for (i = 0; i < pool->pipe_count; i++) {
@@ -360,6 +378,11 @@ static void dcn10_log_color_state(struct dc *dc,
                                s.idle);
        }
        DTN_INFO("\n");
+       DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n",
+                dc->caps.color.mpc.gamut_remap,
+                dc->caps.color.mpc.num_3dluts,
+                dc->caps.color.mpc.ogam_ram,
+                dc->caps.color.mpc.ocsc);
 }
 
 void dcn10_log_hw_state(struct dc *dc,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 24d4e19f90c8aca71605586fb816c895408ae9f4..54d42cf860c93d96a6f39633bc8861ef32606435 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -140,6 +140,24 @@ void dcn30_log_color_state(struct dc *dc,
                DTN_INFO("\n");
        }
        DTN_INFO("\n");
+       DTN_INFO("DPP Color Caps: input_lut_shared:%d  icsc:%d"
+                "  dgam_ram:%d  dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d"
+                "  post_csc:%d  gamcor:%d  dgam_rom_for_yuv:%d  3d_lut:%d"
+                "  blnd_lut:%d  oscs:%d\n\n",
+                dc->caps.color.dpp.input_lut_shared,
+                dc->caps.color.dpp.icsc,
+                dc->caps.color.dpp.dgam_ram,
+                dc->caps.color.dpp.dgam_rom_caps.srgb,
+                dc->caps.color.dpp.dgam_rom_caps.bt2020,
+                dc->caps.color.dpp.dgam_rom_caps.gamma2_2,
+                dc->caps.color.dpp.dgam_rom_caps.pq,
+                dc->caps.color.dpp.dgam_rom_caps.hlg,
+                dc->caps.color.dpp.post_csc,
+                dc->caps.color.dpp.gamma_corr,
+                dc->caps.color.dpp.dgam_rom_for_yuv,
+                dc->caps.color.dpp.hw_3d_lut,
+                dc->caps.color.dpp.ogam_ram,
+                dc->caps.color.dpp.ocsc);
 
        DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE"
                 "  SHAPER mode  3DLUT mode  3DLUT bit-depth  3DLUT size  OGAM mode  OGAM LUT"
@@ -193,6 +211,11 @@ void dcn30_log_color_state(struct dc *dc,
 
        }
        DTN_INFO("\n");
+       DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n",
+                dc->caps.color.mpc.gamut_remap,
+                dc->caps.color.mpc.num_3dluts,
+                dc->caps.color.mpc.ogam_ram,
+                dc->caps.color.mpc.ocsc);
 }
 
 bool dcn30_set_blend_lut(