int layer, struct drm_plane *plane)
 {
        struct drm_plane_state *state = plane->state;
-       struct drm_framebuffer *fb = state->fb;
 
        DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
 
                                                   state->crtc_h));
        }
 
-       /* Set the line width */
-       DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
-       regmap_write(backend->engine.regs,
-                    SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
-                    fb->pitches[0] * 8);
-
        /* Set height and width */
        DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
                         state->crtc_w, state->crtc_h);
        u32 lo_paddr, hi_paddr;
        dma_addr_t paddr;
 
+       /* Set the line width */
+       DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
+       regmap_write(backend->engine.regs,
+                    SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
+                    fb->pitches[0] * 8);
+
        /* Get the start of the displayed memory */
        paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
        DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);