drm/i915/icl: WaAllowUMDToModifySamplerMode

Required for Bindless samplers.
Userspace consumer: mesa

V2: Rebase
V3: Update commit message

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030084504.21537-4-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 41f30207306249c6d1e17bc201106271bafa0a85..aef1a30ff9f6bcfe857e0d2e2e1597d7b4fb6057 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8652,6 +8652,8 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG                 _MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE      (1 << 7)
 
+#define GEN10_SAMPLER_MODE             _MMIO(0xE18C)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)         _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK     (0x7ff << 14)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 8968742788529886c252ea3af007a4cec0c9d3b6..d7176213e3ced315006e882ecc8498bbeb3dcb73 100644 (file)
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1018,6 +1018,9 @@ static void icl_whitelist_build(struct whitelist *w)
 {
        /* WaAllowUMDToModifyHalfSliceChicken7:icl */
        whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+       /* WaAllowUMDToModifySamplerMode:icl */
+       whitelist_reg(w, GEN10_SAMPLER_MODE);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,