Merge tag 'riscv-for-linus-6.11-mw1' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V updates from Palmer Dabbelt:

 - Support for various new ISA extensions:
     * The Zve32[xf] and Zve64[xfd] sub-extensios of the vector
       extension
     * Zimop and Zcmop for may-be-operations
     * The Zca, Zcf, Zcd and Zcb sub-extensions of the C extension
     * Zawrs

 - riscv,cpu-intc is now dtschema

 - A handful of performance improvements and cleanups to text patching

 - Support for memory hot{,un}plug

 - The highest user-allocatable virtual address is now visible in
   hwprobe

* tag 'riscv-for-linus-6.11-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (58 commits)
  riscv: lib: relax assembly constraints in hweight
  riscv: set trap vector earlier
  KVM: riscv: selftests: Add Zawrs extension to get-reg-list test
  KVM: riscv: Support guest wrs.nto
  riscv: hwprobe: export Zawrs ISA extension
  riscv: Add Zawrs support for spinlocks
  dt-bindings: riscv: Add Zawrs ISA extension description
  riscv: Provide a definition for 'pause'
  riscv: hwprobe: export highest virtual userspace address
  riscv: Improve sbi_ecall() code generation by reordering arguments
  riscv: Add tracepoints for SBI calls and returns
  riscv: Optimize crc32 with Zbc extension
  riscv: Enable DAX VMEMMAP optimization
  riscv: mm: Add support for ZONE_DEVICE
  virtio-mem: Enable virtio-mem for RISC-V
  riscv: Enable memory hotplugging for RISC-V
  riscv: mm: Take memory hotplug read-lock during kernel page table dump
  riscv: mm: Add memory hotplugging support
  riscv: mm: Add pfn_to_kaddr() implementation
  riscv: mm: Refactor create_linear_mapping_range() for memory hot add
  ...

diff --cc Documentation/devicetree/bindings/riscv/cpus.yaml
Simple merge

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/include/asm/cmpxchg.h
index 808b4c78462e5aa363fc55d7871497efa23d57b4,637d7acab1f839bf59d36b4b90f9103b7105ae86..ebbce134917ccd26526fcb1dc2a47e3348a041e8
--- 1/arch/riscv/include/asm/cmpxchg.h
--- 2/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@@ -8,9 -8,12 +8,12 @@@
  
  #include <linux/bug.h>
  
+ #include <asm/alternative-macros.h>
  #include <asm/fence.h>
+ #include <asm/hwcap.h>
+ #include <asm/insn-def.h>
  
 -#define __arch_xchg_masked(prepend, append, r, p, n)                  \
 +#define __arch_xchg_masked(sc_sfx, prepend, append, r, p, n)          \
  ({                                                                    \
        u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3);                     \
        ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE;  \

diff --cc arch/riscv/kernel/patch.c
index ab03732d06c46ffec053337c0ba023fa2b2a43c1,5b3f6406e8c44dad160159100fd9cbd2cb8a43f8..69e5796fc51fde6940303514732e16ba72dd574d
--- 1/arch/riscv/kernel/patch.c
--- 2/arch/riscv/kernel/patch.c
+++ b/arch/riscv/kernel/patch.c
@@@ -200,10 -186,11 +202,9 @@@ NOKPROBE_SYMBOL(patch_insn_set)
  
  int patch_text_set_nosync(void *addr, u8 c, size_t len)
  {
-       u32 *tp = addr;
        int ret;
  
-       ret = patch_insn_set(tp, c, len);
+       ret = patch_insn_set(addr, c, len);
 -      if (!ret)
 -              flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len);
  
        return ret;
  }
@@@ -232,10 -222,11 +236,9 @@@ NOKPROBE_SYMBOL(patch_insn_write)
  
  int patch_text_nosync(void *addr, const void *insns, size_t len)
  {
-       u32 *tp = addr;
        int ret;
  
-       ret = patch_insn_write(tp, insns, len);
+       ret = patch_insn_write(addr, insns, len);
 -      if (!ret)
 -              flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len);
  
        return ret;
  }

diff --cc arch/riscv/kvm/vcpu_onereg.c
Simple merge

diff --cc arch/riscv/mm/init.c
Simple merge

diff --cc arch/riscv/net/bpf_jit_comp64.c
index 0795efdd351928a4e964c42132196a11a79fd56f,a01b312913bcd40e3f01ac69630c6ab20d6a61ae..99f34409fb60f48a92366c4824e6237c96f92680
--- 1/arch/riscv/net/bpf_jit_comp64.c
--- 2/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@@ -15,10 -15,8 +15,11 @@@
  #include <asm/percpu.h>
  #include "bpf_jit.h"
  
 +#define RV_MAX_REG_ARGS 8
  #define RV_FENTRY_NINSNS 2
+ #define RV_FENTRY_NBYTES (RV_FENTRY_NINSNS * 4)
 +/* imm that allows emit_imm to emit max count insns */
 +#define RV_MAX_COUNT_IMM 0x7FFF7FF7FF7FF7FF
  
  #define RV_REG_TCC RV_REG_A6
  #define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */