This patch adds a hardware reset the break and overflow bits for
these events. Without resetting the bits they will be reported to
the core every time, when once occur.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
                if (unlikely(sr)) {
                        if (sr & SR_BRK) {
                                port->icount.brk++;
+                               sccnxp_port_write(port, SCCNXP_CR_REG,
+                                                 CR_CMD_BREAK_RESET);
                                if (uart_handle_break(port))
                                        continue;
                        } else if (sr & SR_PE)
                                port->icount.parity++;
                        else if (sr & SR_FE)
                                port->icount.frame++;
-                       else if (sr & SR_OVR)
+                       else if (sr & SR_OVR) {
                                port->icount.overrun++;
+                               sccnxp_port_write(port, SCCNXP_CR_REG,
+                                                 CR_CMD_STATUS_RESET);
+                       }
 
                        sr &= port->read_status_mask;
                        if (sr & SR_BRK)