/* Macros to access registers */
 
-/* Set control for DMA 0 (write only, shadow?) */
-#define RtdDma0Control(dev, n) \
-       writeb(devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0)
-
 /* Get status for DMA 0 */
 #define RtdDma0Status(dev) \
        readb(devpriv->lcfg+LCFG_DMACSR0)
                                DPRINTK
                                    ("rtd520: comedi read buffer overflow (DMA) with %ld to go!\n",
                                     devpriv->aiCount);
-                               RtdDma0Control(dev,
-                                              (devpriv->dma0Control &
-                                               ~PLX_DMA_START_BIT)
-                                              | PLX_CLEAR_DMA_INTR_BIT);
+                               devpriv->dma0Control &= ~PLX_DMA_START_BIT;
+                               devpriv->dma0Control |= PLX_CLEAR_DMA_INTR_BIT;
+                               writeb(devpriv->dma0Control,
+                                       devpriv->lcfg + LCFG_DMACSR0);
                                goto abortTransfer;
                        }
 
                        /*DPRINTK ("rtd520: DMA transfer: %ld to go, istatus %x\n",
                           devpriv->aiCount, istatus); */
-                       RtdDma0Control(dev,
-                                      (devpriv->
-                                       dma0Control & ~PLX_DMA_START_BIT)
-                                      | PLX_CLEAR_DMA_INTR_BIT);
+                       devpriv->dma0Control &= ~PLX_DMA_START_BIT;
+                       devpriv->dma0Control |= PLX_CLEAR_DMA_INTR_BIT;
+                       writeb(devpriv->dma0Control,
+                               devpriv->lcfg + LCFG_DMACSR0);
                        if (0 == devpriv->aiCount) {    /* counted down */
                                DPRINTK("rtd520: Samples Done (DMA).\n");
                                goto transferDone;
                        devpriv->lcfg + LCFG_ITCSR);
                abort_dma(dev, 0);
                devpriv->flags &= ~DMA0_ACTIVE;
-               if (readl(devpriv->lcfg + LCFG_ITCSR) & ICS_DMA0_A)
-                       RtdDma0Control(dev, PLX_CLEAR_DMA_INTR_BIT);
+               if (readl(devpriv->lcfg + LCFG_ITCSR) & ICS_DMA0_A) {
+                       devpriv->dma0Control = PLX_CLEAR_DMA_INTR_BIT;
+                       writeb(devpriv->dma0Control,
+                               devpriv->lcfg + LCFG_DMACSR0);
+               }
        }
        writel(0, devpriv->las0 + LAS0_DMA0_RESET);
 #endif /* USE_DMA */
                writel(readl(devpriv->lcfg + LCFG_ITCSR) | ICS_DMA0_E,
                        devpriv->lcfg + LCFG_ITCSR);
                /* Must be 2 steps.  See PLX app note about "Starting a DMA transfer" */
-               RtdDma0Control(dev, PLX_DMA_EN_BIT);    /* enable DMA (clear INTR?) */
-               RtdDma0Control(dev, PLX_DMA_EN_BIT | PLX_DMA_START_BIT);        /*start DMA */
+               devpriv->dma0Control = PLX_DMA_EN_BIT;
+               writeb(devpriv->dma0Control,
+                       devpriv->lcfg + LCFG_DMACSR0);
+               devpriv->dma0Control |= PLX_DMA_START_BIT;
+               writeb(devpriv->dma0Control,
+                       devpriv->lcfg + LCFG_DMACSR0);
                DPRINTK("rtd520: Using DMA0 transfers. plxInt %x RtdInt %x\n",
                        readl(devpriv->lcfg + LCFG_ITCSR), devpriv->intMask);
 #else /* USE_DMA */
                /* Shut down any board ops by resetting it */
 #ifdef USE_DMA
                if (devpriv->lcfg) {
-                       RtdDma0Control(dev, 0); /* disable DMA */
+                       devpriv->dma0Control = 0;
+                       writeb(devpriv->dma0Control,
+                               devpriv->lcfg + LCFG_DMACSR0);
                        RtdDma1Control(dev, 0); /* disable DMA */
                        writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + LCFG_ITCSR);
                }