drm/msm/mdp5: Separate MDP5 domain from MDSS domain

MDP block is actually contained inside the MDSS block. For some
chipsets, the base address of the MDP registers is different from the
current (assumed) 0x100 offset.

Like CTL and LM blocks, this changes introduce a dynamic offset
for the MDP instance, which can be found out at runtime, once the
MDSS HW version is read.

Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 57d620b4024041a91b3b3d8f20067475a031d9d5..4c570e646b74f6caa9193f822897a48098b6e739 100644 (file)
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -24,6 +24,10 @@ const struct mdp5_cfg_hw *mdp5_cfg = NULL;
 
 const struct mdp5_cfg_hw msm8x74_config = {
        .name = "msm8x74",
+       .mdp = {
+               .count = 1,
+               .base = { 0x00100 },
+       },
        .smp = {
                .mmb_count = 22,
                .mmb_size = 4096,
@@ -75,6 +79,10 @@ const struct mdp5_cfg_hw msm8x74_config = {
 
 const struct mdp5_cfg_hw apq8084_config = {
        .name = "apq8084",
+       .mdp = {
+               .count = 1,
+               .base = { 0x00100 },
+       },
        .smp = {
                .mmb_count = 44,
                .mmb_size = 8192,

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 93bee92e7d6034e8a98420d1502852efe3542c14..11f3e869e880bb320f0d13e7c2c22c967b561a38 100644 (file)
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -61,6 +61,7 @@ struct mdp5_smp_block {
 struct mdp5_cfg_hw {
        char  *name;
 
+       struct mdp5_sub_block mdp;
        struct mdp5_smp_block smp;
        struct mdp5_ctl_block ctl;
        struct mdp5_sub_block pipe_vig;

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 7c0adf54e3e585d883fe0016062a0056d38cb915..0fa7fcefd7eb2880b66513ddbbc2c2ed18689560 100644 (file)
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -112,31 +112,31 @@ static void set_display_intf(struct mdp5_kms *mdp5_kms,
        u32 intf_sel;
 
        spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
-       intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
+       intf_sel = mdp5_read(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0));
 
        switch (intf->num) {
        case 0:
-               intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
-               intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf->type);
+               intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF0__MASK;
+               intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF0(intf->type);
                break;
        case 1:
-               intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
-               intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf->type);
+               intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF1__MASK;
+               intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF1(intf->type);
                break;
        case 2:
-               intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
-               intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf->type);
+               intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF2__MASK;
+               intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF2(intf->type);
                break;
        case 3:
-               intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
-               intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf->type);
+               intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF3__MASK;
+               intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF3(intf->type);
                break;
        default:
                BUG();
                break;
        }
 
-       mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), intf_sel);
        spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
 }
 

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
index a9407105b9b799bea9fc787a923e7dc914bee30a..33bd4c6160dd0ded0fce6f676e02ee803c2572c7 100644 (file)
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
@@ -23,7 +23,7 @@
 
 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask)
 {
-       mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
+       mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_EN(0), irqmask);
 }
 
 static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
@@ -35,8 +35,8 @@ void mdp5_irq_preinstall(struct msm_kms *kms)
 {
        struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
        mdp5_enable(mdp5_kms);
-       mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);
-       mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), 0xffffffff);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000);
        mdp5_disable(mdp5_kms);
 }
 
@@ -61,7 +61,7 @@ void mdp5_irq_uninstall(struct msm_kms *kms)
 {
        struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
        mdp5_enable(mdp5_kms);
-       mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000);
        mdp5_disable(mdp5_kms);
 }
 
@@ -73,8 +73,8 @@ static void mdp5_irq_mdp(struct mdp_kms *mdp_kms)
        unsigned int id;
        uint32_t status;
 
-       status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS);
-       mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);
+       status = mdp5_read(mdp5_kms, REG_MDP5_MDP_INTR_STATUS(0));
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), status);
 
        VERB("status=%08x", status);
 
@@ -91,13 +91,13 @@ irqreturn_t mdp5_irq(struct msm_kms *kms)
        struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
        uint32_t intr;
 
-       intr = mdp5_read(mdp5_kms, REG_MDP5_HW_INTR_STATUS);
+       intr = mdp5_read(mdp5_kms, REG_MDSS_HW_INTR_STATUS);
 
        VERB("intr=%08x", intr);
 
-       if (intr & MDP5_HW_INTR_STATUS_INTR_MDP) {
+       if (intr & MDSS_HW_INTR_STATUS_INTR_MDP) {
                mdp5_irq_mdp(mdp_kms);
-               intr &= ~MDP5_HW_INTR_STATUS_INTR_MDP;
+               intr &= ~MDSS_HW_INTR_STATUS_INTR_MDP;
        }
 
        while (intr) {
@@ -128,10 +128,10 @@ void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  * can register to get their irq's delivered
  */
 
-#define VALID_IRQS  (MDP5_HW_INTR_STATUS_INTR_DSI0 | \
-               MDP5_HW_INTR_STATUS_INTR_DSI1 | \
-               MDP5_HW_INTR_STATUS_INTR_HDMI | \
-               MDP5_HW_INTR_STATUS_INTR_EDP)
+#define VALID_IRQS  (MDSS_HW_INTR_STATUS_INTR_DSI0 | \
+               MDSS_HW_INTR_STATUS_INTR_DSI1 | \
+               MDSS_HW_INTR_STATUS_INTR_HDMI | \
+               MDSS_HW_INTR_STATUS_INTR_EDP)
 
 static void mdp5_hw_mask_irq(struct irq_data *irqd)
 {

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 7e03af56206a537390a1f64ca5f47fd749c473dd..e7ab89dddcf6b65dc53d80c7529e0d8d4167c9c6 100644 (file)
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -58,7 +58,7 @@ static int mdp5_hw_init(struct msm_kms *kms)
         */
 
        spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
-       mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0);
        spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
 
        mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
@@ -296,11 +296,11 @@ static void read_hw_revision(struct mdp5_kms *mdp5_kms,
        uint32_t version;
 
        mdp5_enable(mdp5_kms);
-       version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
+       version = mdp5_read(mdp5_kms, REG_MDSS_HW_VERSION);
        mdp5_disable(mdp5_kms);
 
-       *major = FIELD(version, MDP5_MDP_VERSION_MAJOR);
-       *minor = FIELD(version, MDP5_MDP_VERSION_MINOR);
+       *major = FIELD(version, MDSS_HW_VERSION_MAJOR);
+       *minor = FIELD(version, MDSS_HW_VERSION_MINOR);
 
        DBG("MDP5 version v%d.%d", *major, *minor);
 }
@@ -343,6 +343,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
 
        mdp5_kms->dev = dev;
 
+       /* mdp5_kms->mmio actually represents the MDSS base address */
        mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
        if (IS_ERR(mdp5_kms->mmio)) {
                ret = PTR_ERR(mdp5_kms->mmio);

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
index 690edfde4ba114ecd760130d3462c5a103ff1e5d..6efa5c61aa9809d3492b6f985f84c55fd85d8c47 100644 (file)
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -54,7 +54,7 @@ struct mdp5_kms {
 
        /*
         * lock to protect access to global resources: ie., following register:
-        *      - REG_MDP5_DISP_INTF_SEL
+        *      - REG_MDP5_MDP_DISP_INTF_SEL
         */
        spinlock_t resource_lock;
 

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
index 1f795af89680103211878ac48f77d506981395a6..361c064ba44cc2fc349d162300a981f8c51fe628 100644 (file)
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
@@ -43,7 +43,7 @@
  *     set.
  *
  *  2) mdp5_smp_configure():
- *     As hw is programmed, before FLUSH, MDP5_SMP_ALLOC registers
+ *     As hw is programmed, before FLUSH, MDP5_MDP_SMP_ALLOC registers
  *     are configured for the union(pending, inuse)
  *
  *  3) mdp5_smp_commit():
@@ -237,25 +237,25 @@ static void update_smp_state(struct mdp5_smp *smp,
                int idx = blk / 3;
                int fld = blk % 3;
 
-               val = mdp5_read(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx));
+               val = mdp5_read(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_W_REG(0, idx));
 
                switch (fld) {
                case 0:
-                       val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
-                       val |= MDP5_SMP_ALLOC_W_REG_CLIENT0(cid);
+                       val &= ~MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK;
+                       val |= MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(cid);
                        break;
                case 1:
-                       val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
-                       val |= MDP5_SMP_ALLOC_W_REG_CLIENT1(cid);
+                       val &= ~MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK;
+                       val |= MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(cid);
                        break;
                case 2:
-                       val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
-                       val |= MDP5_SMP_ALLOC_W_REG_CLIENT2(cid);
+                       val &= ~MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK;
+                       val |= MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(cid);
                        break;
                }
 
-               mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx), val);
-               mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(idx), val);
+               mdp5_write(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_W_REG(0, idx), val);
+               mdp5_write(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_R_REG(0, idx), val);
        }
 }