.llseek = default_llseek,
 };
 
+static ssize_t ath10k_debug_fw_reset_stats_read(struct file *file,
+                                               char __user *user_buf,
+                                               size_t count, loff_t *ppos)
+{
+       struct ath10k *ar = file->private_data;
+       int ret, len, buf_len;
+       char *buf;
+
+       buf_len = 500;
+       buf = kmalloc(buf_len, GFP_KERNEL);
+       if (!buf)
+               return -ENOMEM;
+
+       spin_lock_bh(&ar->data_lock);
+
+       len = 0;
+       len += scnprintf(buf + len, buf_len - len,
+                        "fw_crash_counter\t\t%d\n", ar->stats.fw_crash_counter);
+       len += scnprintf(buf + len, buf_len - len,
+                        "fw_warm_reset_counter\t\t%d\n",
+                        ar->stats.fw_warm_reset_counter);
+       len += scnprintf(buf + len, buf_len - len,
+                        "fw_cold_reset_counter\t\t%d\n",
+                        ar->stats.fw_cold_reset_counter);
+
+       spin_unlock_bh(&ar->data_lock);
+
+       ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+
+       kfree(buf);
+
+       return ret;
+}
+
+static const struct file_operations fops_fw_reset_stats = {
+       .open = simple_open,
+       .read = ath10k_debug_fw_reset_stats_read,
+       .owner = THIS_MODULE,
+       .llseek = default_llseek,
+};
+
 /* This is a clean assert crash in firmware. */
 static int ath10k_debug_fw_assert(struct ath10k *ar)
 {
        debugfs_create_file("fw_stats", S_IRUSR, ar->debug.debugfs_phy, ar,
                            &fops_fw_stats);
 
+       debugfs_create_file("fw_reset_stats", S_IRUSR, ar->debug.debugfs_phy,
+                           ar, &fops_fw_reset_stats);
+
        debugfs_create_file("wmi_services", S_IRUSR, ar->debug.debugfs_phy, ar,
                            &fops_wmi_services);
 
 
 
        spin_lock_bh(&ar->data_lock);
 
+       ar->stats.fw_crash_counter++;
+
        crash_data = ath10k_debug_get_new_fw_crash_data(ar);
 
        if (crash_data)
 
        ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
 
+       spin_lock_bh(&ar->data_lock);
+
+       ar->stats.fw_warm_reset_counter++;
+
+       spin_unlock_bh(&ar->data_lock);
+
        /* debug */
        val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
                                PCIE_INTR_CAUSE_ADDRESS);
 
        ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
 
+       spin_lock_bh(&ar->data_lock);
+
+       ar->stats.fw_cold_reset_counter++;
+
+       spin_unlock_bh(&ar->data_lock);
+
        /* Put Target, including PCIe, into RESET. */
        val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
        val |= 1;