arm64/sysreg: Standardise naming for ID_DFR0_EL1

To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.

Ensure symbols for the ID_DFR0_EL1 register have an _EL1 suffix,
and use lower-case for feature names where the arm-arm does the same.

The arm-arm has feature names for some of the ID_DFR0_EL1.PerMon encodings.
Use these feature names in preference to the '8_4' indication of the
architecture version they were introduced in.

No functional change.

Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-12-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 155cb298c89725c87382c25af091432c7dae17c1..835b279f7f200b917fd6ca451bc4edf89900bce9 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -692,12 +692,10 @@
 #define ID_AA64MMFR0_EL1_PARANGE_MAX   ID_AA64MMFR0_EL1_PARANGE_48
 #endif
 
-#define ID_DFR0_PERFMON_SHIFT          24
-
-#define ID_DFR0_PERFMON_8_0            0x3
-#define ID_DFR0_PERFMON_8_1            0x4
-#define ID_DFR0_PERFMON_8_4            0x5
-#define ID_DFR0_PERFMON_8_5            0x6
+#define ID_DFR0_EL1_PerfMon_PMUv3              0x3
+#define ID_DFR0_EL1_PerfMon_PMUv3p1            0x4
+#define ID_DFR0_EL1_PerfMon_PMUv3p4            0x5
+#define ID_DFR0_EL1_PerfMon_PMUv3p5            0x6
 
 #define ID_ISAR4_EL1_SWP_frac_SHIFT            28
 #define ID_ISAR4_EL1_PSR_M_SHIFT               24
@@ -760,13 +758,13 @@
 #define ID_PFR0_EL1_State1_SHIFT       4
 #define ID_PFR0_EL1_State0_SHIFT       0
 
-#define ID_DFR0_PERFMON_SHIFT          24
-#define ID_DFR0_MPROFDBG_SHIFT         20
-#define ID_DFR0_MMAPTRC_SHIFT          16
-#define ID_DFR0_COPTRC_SHIFT           12
-#define ID_DFR0_MMAPDBG_SHIFT          8
-#define ID_DFR0_COPSDBG_SHIFT          4
-#define ID_DFR0_COPDBG_SHIFT           0
+#define ID_DFR0_EL1_PerfMon_SHIFT      24
+#define ID_DFR0_EL1_MProfDbg_SHIFT     20
+#define ID_DFR0_EL1_MMapTrc_SHIFT      16
+#define ID_DFR0_EL1_CopTrc_SHIFT       12
+#define ID_DFR0_EL1_MMapDbg_SHIFT      8
+#define ID_DFR0_EL1_CopSDbg_SHIFT      4
+#define ID_DFR0_EL1_CopDbg_SHIFT       0
 
 #define ID_PFR2_EL1_SSBS_SHIFT         4
 #define ID_PFR2_EL1_CSV3_SHIFT         0

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 8009fc2e4b5ec90efd95f36d93a214a8aa4aa432..77b65a75ba07aef52ad4d59c13cd621e43922ac0 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -567,13 +567,13 @@ static const struct arm64_ftr_bits ftr_id_pfr2[] = {
 
 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
        /* [31:28] TraceFilt */
-       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
+       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f4a7c5abcbca44070292e9a60db6f302acac783d..608e4f25161d3c162feb13bc49abcbbea81fc6b1 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1121,8 +1121,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r
        case SYS_ID_DFR0_EL1:
                /* Limit guests to PMUv3 for ARMv8.4 */
                val = cpuid_feature_cap_perfmon_field(val,
-                                                     ID_DFR0_PERFMON_SHIFT,
-                                                     kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
+                                                     ID_DFR0_EL1_PerfMon_SHIFT,
+                                                     kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_EL1_PerfMon_PMUv3p4 : 0);
                break;
        }