======================================================================
Modifications since 1.2.0:
======================================================================
-
+* Make RAMDisk images work on SMDK2400 / TRAB boards.
+
+* Patch by Pantelis Antoniou, 07 Oct 2002:
+ added support for NetVia board
+
+* Patch by Rod Boyce, 2 Oct 2002:
+ - fixes for some problems on MBX boards
+ - add PCMCIA support for MBX
+
+* Patch by Eran Mann, 01 Oct 2002:
+ - fix support for Marvell EVB-64260-750CX
+
+* Patch by Gerald Van Baren, 04 Oct 2002:
+ - Added sacsng board support
+ - Added soft (bit-banged) SPI driver: this was adapted from the 8xx
+ soft I2C driver.
+ - Added "sspi" command: the stutter on the "ss" is to avoid a
+ command name collision with step(?). To support the spi command,
+ a board-specific chip select array "spi_chipsel_type
+ spi_chipsel[]" is used. This is an array of function pointers,
+ each of which enables/disables the SPI chip select for a given
+ chip. The spi command's <device> parameter is actually the index
+ into this chip select array. Other parameters are <bit_len> and
+ <dout>... they specify how many bits should be shifted out/in and
+ the data to shift out. The nature of SPI is that an equal number
+ of bits get shifted in, which is then displayed. The command
+ isn't pretty, but it can be useful. For an implementation
+ example, see the support in the sacsng board.
+ - Added data line and address line memory tests.
+
+* Use CONFIG_BOOTDELAY as default if "bootdelay" is not set.
+
+* Fix global data access in example code
+
+* Patch by Robert Kaiser, 2 Oct 2002:
+ add "saves" command (dump S-records over serial console)
+
+* Patch by Gary Jennejohn, 01 Oct 2002:
+ - TRAB does not use UART1, so don't configure the I/O pins for it
+ - some pins are used for a different purpose
+ - configure CTS0/RTS0
+
* Run watchdog POST on every power-on
* Fix problems with LWMON's 100 ms watchdog period
UTX8245 MPC8245
+Pantelis Antoniou <panto@intracom.gr>
+
+ NETVIA MPC8xx
+
+Jerry Van Baren <vanbaren_gerald@si.com>
+
+ sacsng MPC8260
+
Oliver Brown <obrown@adventnetworks.com>
sbc8260 MPC8260
IAD210 ICU862_100MHz IP860 IVML24 \
IVML24_128 IVML24_256 IVMS8 IVMS8_128 \
IVMS8_256 LANTEC lwmon MBX \
- MBX860T MHPC MVS1 NX823 \
- pcu_e R360MPI RPXClassic RPXlite \
- SM850 SPD823TS SXNI855T TQM823L \
- TQM823L_LCD TQM850L TQM855L TQM860L \
- TQM860L_FEC TTTech \
+ MBX860T MHPC MVS1 NETVIA \
+ NX823 pcu_e R360MPI RPXClassic \
+ RPXlite SM850 SPD823TS SXNI855T \
+ TQM823L TQM823L_LCD TQM850L TQM855L \
+ TQM860L TQM860L_FEC TTTech \
"
#########################################################################
LIST_8260=" \
cogent_mpc8260 CPU86 ep8260 gw8260 \
hymod IPHASE4539 MPC8260ADS PM826 \
- ppmc8260 RPXsuper rsdproto sbc8260 \
- SCM TQM8260 \
+ ppmc8260 RPXsuper rsdproto sacsng \
+ sbc8260 SCM TQM8260 \
"
#########################################################################
MHPC_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx mhpc eltec
-MVS1_config : unconfig
+MVS1_config : unconfig
@./mkconfig $(@:_config=) ppc mpc8xx mvs1
+NETVIA_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc8xx netvia
+
NX823_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx nx823
rsdproto_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 rsdproto
+sacsng_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc8260 sacsng
+
sbc8260_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 sbc8260
- disk Harddisk interface code
- net Networking code
- ppc Files generic to PowerPC architecture
+- post Power On Self Test
+- post/arch Symlink to architecture specific Power On Self Test
+- post/arch-ppc PowerPC architecture specific Power On Self Test
+- post/cpu/mpc8260 MPC8260 CPU specific Power On Self Test
+- post/cpu/mpc8xx MPC8xx CPU specific Power On Self Test
- rtc Real Time Clock drivers
- tools Tools to build S-Record or PPCBoot images, etc.
- board/sandpoint
Files specific to Sandpoint boards
- board/sbc8260 Files specific to SBC8260 boards
+- board/sacsng Files specific to SACSng boards
- board/siemens Files specific to boards manufactured by Siemens AG
- board/siemens/CCM Files specific to CCM boards
- board/siemens/IAD210 Files specific to IAD210 boards
CONFIG_GENIETV, CONFIG_PM826, CONFIG_ppmc8260,
CONFIG_GTH, CONFIG_RPXClassic, CONFIG_rsdproto,
CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260,
- CONFIG_EBONY
+ CONFIG_EBONY, CONFIG_sacsng
- CPU Module Type: (if CONFIG_COGENT is defined)
CFG_CMD_RUN run command in env variable
CFG_CMD_SCSI * SCSI Support
CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
+ CFG_CMD_SPI * SPI serial bus support
CFG_CMD_USB * USB support
CFG_CMD_BSP * Board SPecific functions
-----------------------------------------------
- SPI Support: CONFIG_SPI
Enables SPI driver (so far only tested with
- SPI EEPROM)
+ SPI EEPROM, also an instance works with Crystal A/D and
+ D/As on the SACSng board)
CONFIG_SPI_X
Enables extended (16-bit) SPI EEPROM addressing.
(symmetrical to CONFIG_I2C_X)
+ CONFIG_SOFT_SPI
+
+ Enables a software (bit-bang) SPI driver rather than
+ using hardware support. This is a general purpose
+ driver that only requires three general I/O port pins
+ (two outputs, one input) to function. If this is
+ defined, the board configuration must define several
+ SPI configuration items (port pins to use, etc). For
+ an example, see include/configs/sacsng.h.
+
- FPGA Support: CONFIG_FPGA_COUNT
Specify the number of FPGA devices to support.
CFG_FPGA_CHECK_BUSY
- Enable checks on FPGA configuration interface busy status
- by the configuration function. This option will require
- a board or device specific function to be written.
+ Enable checks on FPGA configuration interface busy
+ status by the configuration function. This option
+ will require a board or device specific function to
+ be written.
CONFIG_FPGA_DELAY
CFG_FPGA_CHECK_ERROR
- Check for configuration errors during FPGA bitfile loading.
- For example, abort during Virtex II configuration if the
- INIT_B line goes low (which indicated a CRC error).
+ Check for configuration errors during FPGA bitfile
+ loading. For example, abort during Virtex II
+ configuration if the INIT_B line goes low (which
+ indicated a CRC error).
CFG_FPGA_WAIT_INIT
- Maximum time to wait for the INIT_B line to deassert after
- PROB_B has been deasserted during a Virtex II FPGA
- configuration sequence. The default time is 500 mS.
+ Maximum time to wait for the INIT_B line to deassert
+ after PROB_B has been deasserted during a Virtex II
+ FPGA configuration sequence. The default time is 500
+ mS.
CFG_FPGA_WAIT_BUSY
- Maximum time to wait for BUSY to deassert during Virtex II
- FPGA configuration. The default is 5 mS.
+ Maximum time to wait for BUSY to deassert during
+ Virtex II FPGA configuration. The default is 5 mS.
CFG_FPGA_WAIT_CONFIG
- Time to wait after FPGA configuration. The default is 200 mS.
+ Time to wait after FPGA configuration. The default is
+ 200 mS.
- Configuration Management:
CONFIG_IDENT_STRING
Note:
- In the current implementation, the local variables
- space and global environment variables space are
- separated. Local variables are those you define by
- simply typing like `name=value'. To access a local
- variable later on, you have write `$name' or
- `${name}'; variable directly by typing say `$name' at
- the command prompt.
+ In the current implementation, the local variables
+ space and global environment variables space are
+ separated. Local variables are those you define by
+ simply typing like `name=value'. To access a local
+ variable later on, you have write `$name' or
+ `${name}'; variable directly by typing say `$name' at
+ the command prompt.
- Global environment variables are those you use
- setenv/printenv to work with. To run a command stored
- in such a variable, you need to use the run command,
- and you must not use the '$' sign to access them.
+ Global environment variables are those you use
+ setenv/printenv to work with. To run a command stored
+ in such a variable, you need to use the run command,
+ and you must not use the '$' sign to access them.
To store commands and special characters in a
variable, please use double quotation marks
downloaded image) this option may be very useful.
- CFG_FLASH_CFI:
- Define if the flash driver uses extra elements in the common
- flash structure for storing flash geometry
+ Define if the flash driver uses extra elements in the
+ common flash structure for storing flash geometry
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
bootm - boot application image from memory
bootp - boot image via network using BootP/TFTP protocol
tftpboot- boot image via network using TFTP protocol
- and env variables ipaddr and serverip
+ and env variables "ipaddr" and "serverip"
+ (and eventually "gatewayip")
rarpboot- boot image via network using RARP/TFTP protocol
diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd'
loads - load S-Record file over serial line
cp - memory copy
cmp - memory compare
crc32 - checksum calculation
+imd - i2c memory display
+imm - i2c memory modify (auto-incrementing)
+inm - i2c memory modify (constant address)
+imw - i2c memory write (fill)
+icrc32 - i2c checksum calculation
+iprobe - probe to discover valid I2C chip addresses
+iloop - infinite loop on address range
+isdram - print SDRAM configuration information
+sspi - SPI utility commands
base - print or set address offset
printenv- print environment variables
setenv - set environment variables
only effect after the next boot (yes, that's just like Windoze :-).
-Note for Redundand Ethernet Interfaces:
+Note for Redundant Ethernet Interfaces:
=======================================
Some boards come with redundand ethernet interfaces; PPCBoot supports
#ifdef DEBUG
printf("\n%08lx:%08lx:%08lx\n", base, manu, id);
- printf("%08x %08x %08x %08x\n",
+ printf("%08lx %08lx %08lx %08lx\n",
laddr[0],laddr[1],laddr[2],laddr[3]);
#endif
/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
+#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack))
-#define GT_REG_WRITE_MIRROR_G(a,d) {mh->a ## _M = d; GT_REG_WRITE(a,d);}
-#define GTREGREAD_MIRROR_G(a) (mh->a ## _M)
+#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
+#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
-#define GT_REG_WRITE_MIRROR(a,i,g,d) {mh->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);}
-#define GTREGREAD_MIRROR(a,i,g) (mh->a ## _M[i])
+#define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);}
+#define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i])
/* make sure this isn't bigger than 16 long words (ppcboot.h) */
struct _tag_mirror_hack {
unsigned int baudrate; /* current baudrate, for tsc delay calc */
};
-static struct _tag_mirror_hack *const mh =
- (struct _tag_mirror_hack *)(gd_t *)(CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET))->mirror_hack;
-#error Invalid global data initializer
+/* static struct _tag_mirror_hack *mh = NULL; */
/* special function for running out of flash. doesn't modify any
* global variables [josh] */
int
mpsc_putchar_early(char ch)
{
+ DECLARE_GLOBAL_DATA_PTR;
int mpsc=CHANNEL;
int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
galmpsc_set_tcschar(mpsc,ch);
#define MAGIC_FACTOR (10*1000000)
- udelay(MAGIC_FACTOR / mh->baudrate);
+ udelay(MAGIC_FACTOR / MIRROR_HACK->baudrate);
return 0;
}
char
mpsc_getchar(void)
{
+ DECLARE_GLOBAL_DATA_PTR;
static unsigned int done = 0;
volatile char ch;
unsigned int len=0, idx=0, temp;
int
mpsc_init(int baud)
{
- memset(mh, 0, sizeof(struct _tag_mirror_hack));
- mh->GALMPSC_ROUTING_REGISTER_M=0x3fffffff;
+ DECLARE_GLOBAL_DATA_PTR;
+
+ memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack));
+ MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff;
/* BRG CONFIG */
galbrg_set_baudrate(CHANNEL, baud);
int
galbrg_set_baudrate(int channel, int rate)
{
+ DECLARE_GLOBAL_DATA_PTR;
int clock;
galbrg_disable(channel);
galbrg_enable(channel);
- mh->baudrate = rate;
+ MIRROR_HACK->baudrate = rate;
return 0;
}
static int
galbrg_set_CDV(int channel, int value)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
static int
galbrg_enable(int channel)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
static int
galbrg_disable(int channel)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
static int
galbrg_set_clksrc(int channel, int value)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP);
static int
galmpsc_connect(int channel, int connect)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER);
static int
galmpsc_route_rx_clock(int channel, int brg)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE);
static int
galmpsc_route_tx_clock(int channel, int brg)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE);
static int
galmpsc_config_channel_regs(int mpsc)
{
+ DECLARE_GLOBAL_DATA_PTR;
GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0);
GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0);
GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1);
static int
galmpsc_set_brkcnt(int mpsc, int value)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
static int
galmpsc_set_tcschar(int mpsc, int value)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
static int
galmpsc_set_char_length(int mpsc, int value)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
static int
galmpsc_set_stop_bit_length(int mpsc, int value)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
static int
galmpsc_set_parity(int mpsc, int value)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
static int
galmpsc_enter_hunt(int mpsc)
{
+ DECLARE_GLOBAL_DATA_PTR;
int temp;
temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
static int
galmpsc_shutdown(int mpsc)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned int temp;
/* cause RX abort (clears RX) */
uchar trp_clocks, trcd_clocks;
uchar data[128];
- memclk = get_clocks (0);
+ memclk = get_clocks ();
tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
#ifdef CONFIG_EVB64260_750CX
/* DRAM - burst read. (offset 8 in upm RAM)
*/
- 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x00AF0C04,
- 0x07AF0C08, 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C04,
- 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08, 0x0CAF0C04,
- 0x10AF0C04, 0xF0AFC000, 0xF3FF4805, 0xFFFFC005,
+ 0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04,
+ /* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */
+ 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08,
+ 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04,
+ /* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */
+ 0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005,
/* DRAM - single write. (offset 18 in upm RAM)
*/
hang ();
break;
}
+#ifdef CONFIG_USE_PCI
memctl->memc_or5 = CFG_PCIMEM_OR;
memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001;
memctl->memc_or6 = CFG_PCIBRIDGE_OR;
memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001;
+#endif
+ /*
+ * FIXME: I do not understand why I have to call this to
+ * initialise the control register here before booting from
+ * the PCMCIA card but if I do not the Linux kernel falls
+ * over in a big heap. If you can answer this question I
+ * would like to know about it.
+ */
+ board_ether_init();
}
void board_serial_init (void)
static unsigned int board_get_cpufreq (void)
{
+#ifndef CONFIG_8xx_GCLK_FREQ
vpd_packet_t *packet;
packet = vpd_find_packet (VPD_PID_ICS);
return *((ulong *) packet->data);
+#else
+ return((unsigned int)CONFIG_8xx_GCLK_FREQ );
+#endif /* CONFIG_8xx_GCLK_FREQ */
}
static unsigned int get_reffreq (void)
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# netVia Boards
+#
+
+TEXT_BASE = 0x40000000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
+ }
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000);
+ }
+ } else if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_MX:
+ printf("MXIC ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ uchar mid;
+ uchar pid;
+ vu_char *caddr = (vu_char *) addr;
+ ulong base = (ulong) addr;
+
+
+ /* Write auto select command: read Manufacturer ID */
+ caddr[0x0555] = 0xAA;
+ caddr[0x02AA] = 0x55;
+ caddr[0x0555] = 0x90;
+
+ mid = caddr[0];
+ switch (mid) {
+ case (AMD_MANUFACT & 0xFF):
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (FUJ_MANUFACT & 0xFF):
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (MX_MANUFACT & 0xFF):
+ info->flash_id = FLASH_MAN_MX;
+ break;
+ case (STM_MANUFACT & 0xFF):
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ pid = caddr[1]; /* device ID */
+ switch (pid) {
+ case (AMD_ID_LV400T & 0xFF):
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 512 kB */
+
+ case (AMD_ID_LV400B & 0xFF):
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 512 kB */
+
+ case (AMD_ID_LV800T & 0xFF):
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (AMD_ID_LV800B & 0xFF):
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (AMD_ID_LV160T & 0xFF):
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (AMD_ID_LV160B & 0xFF):
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (AMD_ID_LV040B & 0xFF):
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x00080000;
+ break;
+
+ case (STM_ID_M29W040B & 0xFF):
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x00080000;
+ break;
+
+#if 0 /* enable when device IDs are available */
+ case (AMD_ID_LV320T & 0xFF):
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (AMD_ID_LV320B & 0xFF):
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+#endif
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ printf(" ");
+ /* set up sector start address table */
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000);
+ }
+ } else if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection: D0 = 1 if protected */
+ caddr = (volatile unsigned char *)(info->start[i]);
+ info->protect[i] = caddr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ caddr = (vu_char *) info->start[0];
+
+ caddr[0x0555] = 0xAA;
+ caddr[0x02AA] = 0x55;
+ caddr[0x0555] = 0xF0;
+
+ udelay(20000);
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ vu_char *addr = (vu_char *) (info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n", prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0x80;
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_char *) (info->start[sect]);
+ addr[0] = 0x30;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer(0);
+ last = start;
+ addr = (vu_char *) (info->start[l_sect]);
+ while ((addr[0] & 0x80) != 0x80) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+
+ DONE:
+ /* reset to read mode */
+ addr = (vu_char *) info->start[0];
+ addr[0] = 0xF0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ int rc;
+
+ while (cnt > 0) {
+ if ((rc = write_byte(info, addr++, *src++)) != 0) {
+ return (rc);
+ }
+ --cnt;
+ }
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+ vu_char *addr = (vu_char *) (info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_char *) dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0xA0;
+
+ *((vu_char *) dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * PPCboot port on NetVia board
+ */
+
+#include <common.h>
+#include "mpc8xx.h"
+
+/* some sane bit macros */
+#define _BD(_b) (1U << (31-(_b)))
+#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b) (1U << (15-(_b)))
+#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b) (1U << (7-(_b)))
+#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b) _BD(_b)
+#define _BR(_l, _h) _BDR(_l, _h)
+
+/* ------------------------------------------------------------------------- */
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+/* ------------------------------------------------------------------------- */
+
+#define CS_0000 0x00000000
+#define CS_0001 0x10000000
+#define CS_0010 0x20000000
+#define CS_0011 0x30000000
+#define CS_0100 0x40000000
+#define CS_0101 0x50000000
+#define CS_0110 0x60000000
+#define CS_0111 0x70000000
+#define CS_1000 0x80000000
+#define CS_1001 0x90000000
+#define CS_1010 0xA0000000
+#define CS_1011 0xB0000000
+#define CS_1100 0xC0000000
+#define CS_1101 0xD0000000
+#define CS_1110 0xE0000000
+#define CS_1111 0xF0000000
+
+#define BS_0000 0x00000000
+#define BS_0001 0x01000000
+#define BS_0010 0x02000000
+#define BS_0011 0x03000000
+#define BS_0100 0x04000000
+#define BS_0101 0x05000000
+#define BS_0110 0x06000000
+#define BS_0111 0x07000000
+#define BS_1000 0x08000000
+#define BS_1001 0x09000000
+#define BS_1010 0x0A000000
+#define BS_1011 0x0B000000
+#define BS_1100 0x0C000000
+#define BS_1101 0x0D000000
+#define BS_1110 0x0E000000
+#define BS_1111 0x0F000000
+
+#define A10_AAAA 0x00000000
+#define A10_AAA0 0x00200000
+#define A10_AAA1 0x00300000
+#define A10_000A 0x00800000
+#define A10_0000 0x00A00000
+#define A10_0001 0x00B00000
+#define A10_111A 0x00C00000
+#define A10_1110 0x00E00000
+#define A10_1111 0x00F00000
+
+#define RAS_0000 0x00000000
+#define RAS_0001 0x00040000
+#define RAS_1110 0x00080000
+#define RAS_1111 0x000C0000
+
+#define CAS_0000 0x00000000
+#define CAS_0001 0x00010000
+#define CAS_1110 0x00020000
+#define CAS_1111 0x00030000
+
+#define WE_0000 0x00000000
+#define WE_0001 0x00004000
+#define WE_1110 0x00008000
+#define WE_1111 0x0000C000
+
+#define GPL4_0000 0x00000000
+#define GPL4_0001 0x00001000
+#define GPL4_1110 0x00002000
+#define GPL4_1111 0x00003000
+
+#define GPL5_0000 0x00000000
+#define GPL5_0001 0x00000400
+#define GPL5_1110 0x00000800
+#define GPL5_1111 0x00000C00
+#define LOOP 0x00000080
+
+#define EXEN 0x00000040
+
+#define AMX_COL 0x00000000
+#define AMX_ROW 0x00000020
+#define AMX_MAR 0x00000030
+
+#define NA 0x00000008
+
+#define UTA 0x00000004
+
+#define TODT 0x00000002
+
+#define LAST 0x00000001
+
+const uint sdram_table[0x40] = {
+ /* RSS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_,
+
+ /* RBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WSS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
+ CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* UPT */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP,
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP,
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_,
+
+ /* EXC */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,
+
+ /* REG */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR,
+ CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ETX ID string (ETX_xxx...)
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+ printf ("NETVIA\n");
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+#define MAR_SDRAM_INIT 0x000000C8LU
+
+#define MCR_OP(x) ((unsigned long)((x) & 3) << (31-1))
+#define MCR_OP_MASK MCR_OP(3)
+
+#define MCR_UM(x) ((unsigned long)((x) & 1) << (31 - 8))
+#define MCR_UM_MASK MCR_UM(1)
+#define MCR_UM_UPMA MCR_UM(0)
+#define MCR_UM_UPMB MCR_UM(1)
+
+#define MCR_MB(x) ((unsigned long)((x) & 7) << (31 - 18))
+#define MCR_MB_MASK MCR_MB(7)
+#define MCR_MB_CS(x) MCR_MB(x)
+
+#define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23))
+#define MCR_MCLF_MASK MCR_MCLF(15)
+
+long int initdram(int board_type)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size;
+
+ upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+ /*
+ * Preliminary prescaler for refresh
+ */
+ memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+
+ memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
+
+ memctl->memc_mamr = CFG_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */
+
+ udelay(200);
+
+ /* perform SDRAM initialisation sequence */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C); /* precharge all */
+ udelay(1);
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0) */
+ udelay(1);
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E); /* exception program (write mar) */
+ udelay(1);
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay(1000);
+
+ memctl->memc_mamr = CFG_MAMR_9COL;
+
+ size = SDRAM_MAX_SIZE;
+
+ udelay(10000);
+
+ /* do the ram test */
+ {
+ register unsigned long *rp;
+ register unsigned long v;
+
+ /* first fill */
+ for (rp = (unsigned long *)0; rp < (unsigned long *)SDRAM_MAX_SIZE; )
+ *rp++ = (unsigned long)rp;
+
+ /* now check */
+ for (rp = (unsigned long *)0; rp < (unsigned long *)SDRAM_MAX_SIZE; rp++) {
+ if ((v = *rp) != (unsigned long)rp) {
+ printf("ERROR at 0x%lx (0x%lx)\n", (unsigned long)rp, v);
+ return -1;
+ }
+ }
+
+ }
+
+ return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r(void)
+{
+ return(0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_MASK (_BWR(4, 9) | _BWR(12, 15))
+#define PA_ODR_MASK (_BW(9) | _BW(12) | _BW(14))
+#define PA_ODR_VAL 0
+#define PA_GP_INMASK 0
+#define PA_GP_OUTMASK (_BW(5) | _BW(14) | _BW(15))
+#define PA_SP_OUTMASK 0
+#define PA_GP_OUTVAL _BW(5)
+#define PA_SP_OUTVAL 0
+
+#define PB_MASK (_BR(16, 19) | _BR(22, 31))
+#define PB_ODR_MASK PB_MASK
+#define PB_ODR_VAL 0
+#define PB_GP_INMASK 0
+#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _B(31))
+#define PB_SP_OUTMASK _BR(28, 30)
+#define PB_SP_OUTVAL _BR(28, 30)
+#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _B(31))
+
+#define PC_MASK _BWR(4, 15)
+#define PC_SO_MASK (_BWR(6, 11) | _BWR(14, 15))
+#define PC_SO_VAL 0
+#define PC_INT_MASK PC_MASK
+#define PC_INT_VAL 0
+#define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13))
+#define PC_GP_OUTMASK _BW(12)
+#define PC_SP_OUTMASK 0
+#define PC_SP_OUTVAL _BW(12)
+#define PC_GP_OUTVAL 0
+
+#define PD_MASK _BWR(0, 15)
+#define PD_GP_INMASK 0
+#define PD_GP_OUTMASK _BWR(3, 15)
+#define PD_SP_OUTMASK 0
+#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15))
+#define PD_SP_OUTVAL 0
+
+int board_pre_init(void)
+{
+ register volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ register volatile iop8xx_t *ioport = &immap->im_ioport;
+ register volatile cpm8xx_t *cpm = &immap->im_cpm;
+
+ ioport->iop_padat = (ioport->iop_padat & ~PA_MASK) | PA_SP_OUTVAL | PA_GP_OUTVAL;
+ ioport->iop_paodr = (ioport->iop_paodr & ~PA_ODR_MASK) | PA_ODR_VAL;
+ ioport->iop_padir = (ioport->iop_padir & ~PA_GP_INMASK)| PA_SP_OUTMASK | PA_GP_OUTMASK;
+ ioport->iop_papar = (ioport->iop_papar & ~(PA_GP_INMASK & PA_GP_OUTMASK));
+
+ cpm->cp_pbdat = (ioport->iop_padat & ~PB_MASK) | PB_SP_OUTVAL | PB_GP_OUTVAL;
+ cpm->cp_pbodr = (ioport->iop_paodr & ~PB_ODR_MASK) | PB_ODR_VAL;
+ cpm->cp_pbdir = (ioport->iop_padir & ~PB_GP_INMASK)| PB_SP_OUTMASK | PB_GP_OUTMASK;
+ cpm->cp_pbpar = (ioport->iop_papar & ~(PB_GP_INMASK & PB_GP_OUTMASK));
+
+ ioport->iop_pcdat = (ioport->iop_pcdat & ~PC_MASK) | PC_SP_OUTVAL | PC_GP_OUTVAL;
+ ioport->iop_pcdir = (ioport->iop_pcdir & ~PC_GP_INMASK)| PC_SP_OUTMASK | PC_GP_OUTMASK;
+ ioport->iop_pcso = (ioport->iop_pcso & ~PC_SO_MASK) | PC_SO_VAL;
+ ioport->iop_pcint = (ioport->iop_pcint & ~PC_INT_MASK) | PC_INT_VAL;
+ ioport->iop_pcpar = (ioport->iop_pcpar & ~(PC_GP_INMASK & PC_GP_OUTMASK));
+
+ ioport->iop_pddat = (ioport->iop_pddat & ~PD_MASK) | PD_SP_OUTVAL | PD_GP_OUTVAL;
+ ioport->iop_pddir = (ioport->iop_pddir & ~PD_GP_INMASK)| PD_SP_OUTMASK | PD_GP_OUTMASK;
+ ioport->iop_pdpar = (ioport->iop_pdpar & ~(PD_GP_INMASK & PD_GP_OUTMASK));
+
+ return 0;
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ cpu/mpc8xx/traps.o (.text)
+ common/dlmalloc.o (.text)
+ lib_ppc/ppcstring.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ lib_ppc/cache.o (.text)
+ lib_ppc/time.o (.text)
+
+ . = env_offset;
+ common/environment.o (.ppcenv)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
+ reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
udelay (10000);
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
+ ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
+ addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := sacsng.o flash.o clkinit.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Jon Diekema <diekema@cideas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/cpm_8260.h>
+#include <configs/sacsng.h>
+
+#include "clkinit.h"
+
+int Daq64xSampling = 0;
+
+
+void Daq_BRG_Reset(uint brg)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile uint *brg_ptr;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ brg_ptr += brg;
+ *brg_ptr |= CPM_BRG_RST;
+ *brg_ptr &= ~CPM_BRG_RST;
+}
+
+void Daq_BRG_Disable(uint brg)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile uint *brg_ptr;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ brg_ptr += brg;
+ *brg_ptr &= ~CPM_BRG_EN;
+}
+
+void Daq_BRG_Enable(uint brg)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile uint *brg_ptr;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ brg_ptr += brg;
+ *brg_ptr |= CPM_BRG_EN;
+}
+
+uint Daq_BRG_Get_Div16(uint brg)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uint *brg_ptr;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ brg_ptr += brg;
+
+ if (*brg_ptr & CPM_BRG_DIV16) {
+ /* DIV16 active */
+ return (TRUE);
+ }
+ else {
+ /* DIV16 inactive */
+ return (FALSE);
+ }
+}
+
+void Daq_BRG_Set_Div16(uint brg, uint div16)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uint *brg_ptr;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ brg_ptr += brg;
+
+ if (div16) {
+ /* DIV16 active */
+ *brg_ptr |= CPM_BRG_DIV16;
+ }
+ else {
+ /* DIV16 inactive */
+ *brg_ptr &= ~CPM_BRG_DIV16;
+ }
+}
+
+uint Daq_BRG_Get_Count(uint brg)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uint *brg_ptr;
+ uint brg_cnt;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ brg_ptr += brg;
+
+ /* Get the clock divider
+ *
+ * Note: A clock divider of 0 means divide by 1,
+ * therefore we need to add 1 to the count.
+ */
+ brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
+ brg_cnt++;
+ if (*brg_ptr & CPM_BRG_DIV16) {
+ brg_cnt *= 16;
+ }
+
+ return (brg_cnt);
+}
+
+void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uint *brg_ptr;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ brg_ptr += brg;
+
+ /*
+ * Note: A clock divider of 0 means divide by 1,
+ * therefore we need to subtract 1 from the count.
+ */
+ if (brg_cnt > 4096) {
+ /* Prescale = Divide by 16 */
+ *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
+ (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
+ *brg_ptr |= CPM_BRG_DIV16;
+ }
+ else {
+ /* Prescale = Divide by 1 */
+ *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
+ ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
+ *brg_ptr &= ~CPM_BRG_DIV16;
+ }
+}
+
+uint Daq_BRG_Get_ExtClk(uint brg)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uint *brg_ptr;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ brg_ptr += brg;
+
+ return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
+}
+
+char* Daq_BRG_Get_ExtClk_Description(uint brg)
+{
+ uint extc;
+
+ extc = Daq_BRG_Get_ExtClk(brg);
+
+ switch (brg + 1) {
+ case 1:
+ case 2:
+ case 5:
+ case 6: {
+ switch (extc) {
+ case 0: {
+ return ("BRG_INT");
+ }
+ case 1: {
+ return ("CLK3");
+ }
+ case 2: {
+ return ("CLK5");
+ }
+ }
+ return ("??1245??");
+ }
+ case 3:
+ case 4:
+ case 7:
+ case 8: {
+ switch (extc) {
+ case 0: {
+ return ("BRG_INT");
+ }
+ case 1: {
+ return ("CLK9");
+ }
+ case 2: {
+ return ("CLK15");
+ }
+ }
+ return ("??3478??");
+ }
+ }
+ return ("??9876??");
+}
+
+void Daq_BRG_Set_ExtClk(uint brg, uint extc)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uint *brg_ptr;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ brg_ptr += brg;
+
+ *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
+ ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
+}
+
+uint Daq_BRG_Rate(uint brg)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uint *brg_ptr;
+ uint brg_cnt;
+ uint brg_freq = 0;
+
+ brg_ptr = (uint *)&immr->im_brgc1;
+ brg_ptr += brg;
+ if (brg >= 5) {
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg_ptr += (brg - 4);
+ }
+
+ brg_cnt = Daq_BRG_Get_Count(brg);
+
+ switch (Daq_BRG_Get_ExtClk(brg)) {
+ case CPM_BRG_EXTC_CLK3:
+ case CPM_BRG_EXTC_CLK5: {
+ brg_freq = brg_cnt;
+ break;
+ }
+ default: {
+ brg_freq = (uint)BRG_INT_CLK / brg_cnt;
+ }
+ }
+ return (brg_freq);
+}
+
+uint Daq_Get_SampleRate(void)
+
+{
+ /*
+ * Read the BRG's to return the actual sample rate.
+ */
+ return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
+}
+
+uint Daq_Set_SampleRate(uint rate, uint force)
+
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ uint mclk_divisor; /* MCLK divisor */
+ uint rate_curr; /* Current sample rate */
+
+ /*
+ * Limit the sample rate to some sensible values.
+ */
+ if (Daq64xSampling) {
+ if (rate > MAX_64x_SAMPLE_RATE) {
+ rate = MAX_64x_SAMPLE_RATE;
+ }
+ }
+ else {
+ if (rate > MAX_128x_SAMPLE_RATE) {
+ rate = MAX_128x_SAMPLE_RATE;
+ }
+ }
+ if (rate < MIN_SAMPLE_RATE) {
+ rate = MIN_SAMPLE_RATE;
+ }
+
+ /* Check to see if we are really changing rates */
+ rate_curr = Daq_Get_SampleRate();
+ if ((rate != rate_curr) || force) {
+ /*
+ * Dynamically adjust MCLK based on the new sample rate.
+ */
+
+ /* Compute the divisors */
+ mclk_divisor = BRG_INT_CLK / (rate * MCLK_DIVISOR * SCLK_DIVISOR);
+
+ /* Setup MCLK */
+ Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
+
+ /* Setup SCLK */
+# ifdef RUN_SCLK_ON_BRG_INT
+ Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
+# else
+ Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
+# endif
+
+# ifdef RUN_LRCLK_ON_BRG_INT
+ Daq_BRG_Set_Count(LRCLK_BRG,
+ mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
+# else
+ Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
+# endif
+
+ /* Read the BRG's to return the actual sample rate. */
+ rate_curr = Daq_Get_SampleRate();
+ }
+
+ return (rate_curr);
+}
+
+void Daq_Init_Clocks(int sample_rate, int sample_64x)
+
+{
+ volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
+
+ /* Save off the clocking data */
+ Daq64xSampling = sample_64x;
+
+ /*
+ * Limit the sample rate to some sensible values.
+ */
+ if (Daq64xSampling) {
+ if (sample_rate > MAX_64x_SAMPLE_RATE) {
+ sample_rate = MAX_64x_SAMPLE_RATE;
+ }
+ }
+ else {
+ if (sample_rate > MAX_128x_SAMPLE_RATE) {
+ sample_rate = MAX_128x_SAMPLE_RATE;
+ }
+ }
+ if (sample_rate < MIN_SAMPLE_RATE) {
+ sample_rate = MIN_SAMPLE_RATE;
+ }
+
+ /*
+ * Initialize the MCLK/SCLK/LRCLK baud rate generators.
+ */
+
+ /* Setup MCLK */
+ Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+
+ /* Setup SCLK */
+# ifdef RUN_SCLK_ON_BRG_INT
+ Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+# else
+ Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
+# endif
+
+ /* Setup LRCLK */
+# ifdef RUN_LRCLK_ON_BRG_INT
+ Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+# else
+ Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
+# endif
+
+ /* Setup the BRG rates */
+ Daq_Set_SampleRate(sample_rate, TRUE);
+
+ /* Enable the clock drivers */
+ iopa->pdat &= ~SLRCLK_EN_MASK;
+}
+
+void Daq_Stop_Clocks(void)
+
+{
+#ifdef TIGHTEN_UP_BRG_TIMING
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
+
+# ifdef TIGHTEN_UP_BRG_TIMING
+ /*
+ * Reset MCLK BRG
+ */
+# if (MCLK_BRG == 0)
+ immr->im_brgc1 |= CPM_BRG_RST;
+ immr->im_brgc1 &= ~CPM_BRG_RST;
+# endif
+# if (MCLK_BRG == 1)
+ immr->im_brgc2 |= CPM_BRG_RST;
+ immr->im_brgc2 &= ~CPM_BRG_RST;
+# endif
+# if (MCLK_BRG == 2)
+ immr->im_brgc3 |= CPM_BRG_RST;
+ immr->im_brgc3 &= ~CPM_BRG_RST;
+# endif
+# if (MCLK_BRG == 3)
+ immr->im_brgc4 |= CPM_BRG_RST;
+ immr->im_brgc4 &= ~CPM_BRG_RST;
+# endif
+# if (MCLK_BRG == 4)
+ immr->im_brgc5 |= CPM_BRG_RST;
+ immr->im_brgc5 &= ~CPM_BRG_RST;
+# endif
+# if (MCLK_BRG == 5)
+ immr->im_brgc6 |= CPM_BRG_RST;
+ immr->im_brgc6 &= ~CPM_BRG_RST;
+# endif
+# if (MCLK_BRG == 6)
+ immr->im_brgc7 |= CPM_BRG_RST;
+ immr->im_brgc7 &= ~CPM_BRG_RST;
+# endif
+# if (MCLK_BRG == 7)
+ immr->im_brgc8 |= CPM_BRG_RST;
+ immr->im_brgc8 &= ~CPM_BRG_RST;
+# endif
+
+ /*
+ * Reset SCLK BRG
+ */
+# if (SCLK_BRG == 0)
+ immr->im_brgc1 |= CPM_BRG_RST;
+ immr->im_brgc1 &= ~CPM_BRG_RST;
+# endif
+# if (SCLK_BRG == 1)
+ immr->im_brgc2 |= CPM_BRG_RST;
+ immr->im_brgc2 &= ~CPM_BRG_RST;
+# endif
+# if (SCLK_BRG == 2)
+ immr->im_brgc3 |= CPM_BRG_RST;
+ immr->im_brgc3 &= ~CPM_BRG_RST;
+# endif
+# if (SCLK_BRG == 3)
+ immr->im_brgc4 |= CPM_BRG_RST;
+ immr->im_brgc4 &= ~CPM_BRG_RST;
+# endif
+# if (SCLK_BRG == 4)
+ immr->im_brgc5 |= CPM_BRG_RST;
+ immr->im_brgc5 &= ~CPM_BRG_RST;
+# endif
+# if (SCLK_BRG == 5)
+ immr->im_brgc6 |= CPM_BRG_RST;
+ immr->im_brgc6 &= ~CPM_BRG_RST;
+# endif
+# if (SCLK_BRG == 6)
+ immr->im_brgc7 |= CPM_BRG_RST;
+ immr->im_brgc7 &= ~CPM_BRG_RST;
+# endif
+# if (SCLK_BRG == 7)
+ immr->im_brgc8 |= CPM_BRG_RST;
+ immr->im_brgc8 &= ~CPM_BRG_RST;
+# endif
+
+ /*
+ * Reset LRCLK BRG
+ */
+# if (LRCLK_BRG == 0)
+ immr->im_brgc1 |= CPM_BRG_RST;
+ immr->im_brgc1 &= ~CPM_BRG_RST;
+# endif
+# if (LRCLK_BRG == 1)
+ immr->im_brgc2 |= CPM_BRG_RST;
+ immr->im_brgc2 &= ~CPM_BRG_RST;
+# endif
+# if (LRCLK_BRG == 2)
+ immr->im_brgc3 |= CPM_BRG_RST;
+ immr->im_brgc3 &= ~CPM_BRG_RST;
+# endif
+# if (LRCLK_BRG == 3)
+ immr->im_brgc4 |= CPM_BRG_RST;
+ immr->im_brgc4 &= ~CPM_BRG_RST;
+# endif
+# if (LRCLK_BRG == 4)
+ immr->im_brgc5 |= CPM_BRG_RST;
+ immr->im_brgc5 &= ~CPM_BRG_RST;
+# endif
+# if (LRCLK_BRG == 5)
+ immr->im_brgc6 |= CPM_BRG_RST;
+ immr->im_brgc6 &= ~CPM_BRG_RST;
+# endif
+# if (LRCLK_BRG == 6)
+ immr->im_brgc7 |= CPM_BRG_RST;
+ immr->im_brgc7 &= ~CPM_BRG_RST;
+# endif
+# if (LRCLK_BRG == 7)
+ immr->im_brgc8 |= CPM_BRG_RST;
+ immr->im_brgc8 &= ~CPM_BRG_RST;
+# endif
+# else
+ /*
+ * Reset the clocks
+ */
+ Daq_BRG_Reset(MCLK_BRG);
+ Daq_BRG_Reset(SCLK_BRG);
+ Daq_BRG_Reset(LRCLK_BRG);
+# endif
+}
+
+void Daq_Start_Clocks(int sample_rate)
+
+{
+#ifdef TIGHTEN_UP_BRG_TIMING
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ uint mclk_brg; /* MCLK BRG value */
+ uint sclk_brg; /* SCLK BRG value */
+ uint lrclk_brg; /* LRCLK BRG value */
+ uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
+ uint real_lrclk_brg; /* Permanent LRCLK BRG value */
+ unsigned long flags; /* Interrupt flags */
+ uint sclk_cnt; /* SCLK count */
+ uint delay_cnt; /* Delay count */
+#endif
+
+# ifdef TIGHTEN_UP_BRG_TIMING
+ /*
+ * Obtain the enabled MCLK BRG value
+ */
+# if (MCLK_BRG == 0)
+ mclk_brg = (immr->im_brgc1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (MCLK_BRG == 1)
+ mclk_brg = (immr->im_brgc2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (MCLK_BRG == 2)
+ mclk_brg = (immr->im_brgc3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (MCLK_BRG == 3)
+ mclk_brg = (immr->im_brgc4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (MCLK_BRG == 4)
+ mclk_brg = (immr->im_brgc5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (MCLK_BRG == 5)
+ mclk_brg = (immr->im_brgc6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (MCLK_BRG == 6)
+ mclk_brg = (immr->im_brgc7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (MCLK_BRG == 7)
+ mclk_brg = (immr->im_brgc8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+
+ /*
+ * Obtain the enabled SCLK BRG value
+ */
+# if (SCLK_BRG == 0)
+ sclk_brg = (immr->im_brgc1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (SCLK_BRG == 1)
+ sclk_brg = (immr->im_brgc2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (SCLK_BRG == 2)
+ sclk_brg = (immr->im_brgc3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (SCLK_BRG == 3)
+ sclk_brg = (immr->im_brgc4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (SCLK_BRG == 4)
+ sclk_brg = (immr->im_brgc5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (SCLK_BRG == 5)
+ sclk_brg = (immr->im_brgc6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (SCLK_BRG == 6)
+ sclk_brg = (immr->im_brgc7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (SCLK_BRG == 7)
+ sclk_brg = (immr->im_brgc8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+
+ /*
+ * Obtain the enabled LRCLK BRG value
+ */
+# if (LRCLK_BRG == 0)
+ lrclk_brg = (immr->im_brgc1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (LRCLK_BRG == 1)
+ lrclk_brg = (immr->im_brgc2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (LRCLK_BRG == 2)
+ lrclk_brg = (immr->im_brgc3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (LRCLK_BRG == 3)
+ lrclk_brg = (immr->im_brgc4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (LRCLK_BRG == 4)
+ lrclk_brg = (immr->im_brgc5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (LRCLK_BRG == 5)
+ lrclk_brg = (immr->im_brgc6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (LRCLK_BRG == 6)
+ lrclk_brg = (immr->im_brgc7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+# if (LRCLK_BRG == 7)
+ lrclk_brg = (immr->im_brgc8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+# endif
+
+ /* Save off the real LRCLK value */
+ real_lrclk_brg = lrclk_brg;
+
+ /* Obtain the current SCLK count */
+ sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1;
+
+ /* Compute the delay as a function of SCLK count */
+ delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
+ if (sample_rate == 43402) {
+ delay_cnt++;
+ }
+
+ /* Clear out the count */
+ temp_lrclk_brg = sclk_brg & ~0x00001FFE;
+
+ /* Insert the count */
+ temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE;
+
+ /*
+ * Enable MCLK BRG
+ */
+# if (MCLK_BRG == 0)
+ immr->im_brgc1 = mclk_brg;
+# endif
+# if (MCLK_BRG == 1)
+ immr->im_brgc2 = mclk_brg;
+# endif
+# if (MCLK_BRG == 2)
+ immr->im_brgc3 = mclk_brg;
+# endif
+# if (MCLK_BRG == 3)
+ immr->im_brgc4 = mclk_brg;
+# endif
+# if (MCLK_BRG == 4)
+ immr->im_brgc5 = mclk_brg;
+# endif
+# if (MCLK_BRG == 5)
+ immr->im_brgc6 = mclk_brg;
+# endif
+# if (MCLK_BRG == 6)
+ immr->im_brgc7 = mclk_brg;
+# endif
+# if (MCLK_BRG == 7)
+ immr->im_brgc8 = mclk_brg;
+# endif
+
+ /*
+ * Enable SCLK BRG
+ */
+# if (SCLK_BRG == 0)
+ immr->im_brgc1 = sclk_brg;
+# endif
+# if (SCLK_BRG == 1)
+ immr->im_brgc2 = sclk_brg;
+# endif
+# if (SCLK_BRG == 2)
+ immr->im_brgc3 = sclk_brg;
+# endif
+# if (SCLK_BRG == 3)
+ immr->im_brgc4 = sclk_brg;
+# endif
+# if (SCLK_BRG == 4)
+ immr->im_brgc5 = sclk_brg;
+# endif
+# if (SCLK_BRG == 5)
+ immr->im_brgc6 = sclk_brg;
+# endif
+# if (SCLK_BRG == 6)
+ immr->im_brgc7 = sclk_brg;
+# endif
+# if (SCLK_BRG == 7)
+ immr->im_brgc8 = sclk_brg;
+# endif
+
+ /*
+ * Enable LRCLK BRG (1st time - temporary)
+ */
+# if (LRCLK_BRG == 0)
+ immr->im_brgc1 = temp_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 1)
+ immr->im_brgc2 = temp_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 2)
+ immr->im_brgc3 = temp_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 3)
+ immr->im_brgc4 = temp_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 4)
+ immr->im_brgc5 = temp_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 5)
+ immr->im_brgc6 = temp_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 6)
+ immr->im_brgc7 = temp_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 7)
+ immr->im_brgc8 = temp_lrclk_brg;
+# endif
+
+ /*
+ * Enable LRCLK BRG (2nd time - permanent)
+ */
+# if (LRCLK_BRG == 0)
+ immr->im_brgc1 = real_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 1)
+ immr->im_brgc2 = real_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 2)
+ immr->im_brgc3 = real_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 3)
+ immr->im_brgc4 = real_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 4)
+ immr->im_brgc5 = real_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 5)
+ immr->im_brgc6 = real_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 6)
+ immr->im_brgc7 = real_lrclk_brg;
+# endif
+# if (LRCLK_BRG == 7)
+ immr->im_brgc8 = real_lrclk_brg;
+# endif
+# else
+ /*
+ * Enable the clocks
+ */
+ Daq_BRG_Enable(LRCLK_BRG);
+ Daq_BRG_Enable(SCLK_BRG);
+ Daq_BRG_Enable(MCLK_BRG);
+# endif
+}
+
+void Daq_Display_Clocks(void)
+
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uint mclk_divisor; /* Detected MCLK divisor */
+ uint sclk_divisor; /* Detected SCLK divisor */
+
+ printf("\nBRG:\n");
+ if (immr->im_brgc4 != 0) {
+ printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
+ immr->im_brgc4,
+ (uint)&(immr->im_brgc4),
+ Daq_BRG_Get_Count(3),
+ Daq_BRG_Get_ExtClk(3),
+ Daq_BRG_Get_ExtClk_Description(3));
+ }
+ if (immr->im_brgc8 != 0) {
+ printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
+ immr->im_brgc8,
+ (uint)&(immr->im_brgc8),
+ Daq_BRG_Get_Count(7),
+ Daq_BRG_Get_ExtClk(7),
+ Daq_BRG_Get_ExtClk_Description(7));
+ }
+ if (immr->im_brgc6 != 0) {
+ printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
+ immr->im_brgc6,
+ (uint)&(immr->im_brgc6),
+ Daq_BRG_Get_Count(5),
+ Daq_BRG_Get_ExtClk(5),
+ Daq_BRG_Get_ExtClk_Description(5));
+ }
+ if (immr->im_brgc1 != 0) {
+ printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
+ immr->im_brgc1,
+ (uint)&(immr->im_brgc1),
+ Daq_BRG_Get_Count(0),
+ Daq_BRG_Get_ExtClk(0),
+ Daq_BRG_Get_ExtClk_Description(0));
+ }
+ if (immr->im_brgc2 != 0) {
+ printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
+ immr->im_brgc2,
+ (uint)&(immr->im_brgc2),
+ Daq_BRG_Get_Count(1),
+ Daq_BRG_Get_ExtClk(1),
+ Daq_BRG_Get_ExtClk_Description(1));
+ }
+ if (immr->im_brgc3 != 0) {
+ printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
+ immr->im_brgc3,
+ (uint)&(immr->im_brgc3),
+ Daq_BRG_Get_Count(2),
+ Daq_BRG_Get_ExtClk(2),
+ Daq_BRG_Get_ExtClk_Description(2));
+ }
+ if (immr->im_brgc5 != 0) {
+ printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+ immr->im_brgc5,
+ (uint)&(immr->im_brgc5),
+ Daq_BRG_Get_Count(4),
+ Daq_BRG_Get_ExtClk(4),
+ Daq_BRG_Get_ExtClk_Description(4));
+ }
+ if (immr->im_brgc7 != 0) {
+ printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+ immr->im_brgc7,
+ (uint)&(immr->im_brgc7),
+ Daq_BRG_Get_Count(6),
+ Daq_BRG_Get_ExtClk(6),
+ Daq_BRG_Get_ExtClk_Description(6));
+ }
+
+# ifdef RUN_SCLK_ON_BRG_INT
+ mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
+# else
+ mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
+# endif
+# ifdef RUN_LRCLK_ON_BRG_INT
+ sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
+# else
+ sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
+# endif
+
+ printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
+ printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
+ Daq_BRG_Rate(MCLK_BRG),
+ mclk_divisor,
+ mclk_divisor * sclk_divisor);
+# ifdef RUN_SCLK_ON_BRG_INT
+ printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
+ Daq_BRG_Rate(SCLK_BRG),
+ sclk_divisor);
+# else
+ printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
+ Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
+ sclk_divisor);
+# endif
+# ifdef RUN_LRCLK_ON_BRG_INT
+ printf("\tLRCLK %8d Hz\n",
+ Daq_BRG_Rate(LRCLK_BRG));
+# else
+# ifdef RUN_SCLK_ON_BRG_INT
+ printf("\tLRCLK %8d Hz\n",
+ Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
+# else
+ printf("\tLRCLK %8d Hz\n",
+ Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
+# endif
+# endif
+ printf("\n");
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Jon Diekema <diekema@cideas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE (!FALSE)
+#endif
+
+#define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */
+
+#define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */
+#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
+#define MAX_64x_SAMPLE_RATE 86805 /* Maximum 64x sample rate */
+
+#define KHZ ((uint)1000)
+#define MHZ ((uint)(1000 * KHZ))
+
+#define MCLK_BRG 3 /* MCLK, Master CLocK for the A/D & D/A */
+#define SCLK_BRG 7 /* SCLK, Sample CLocK for the A/D & D/A */
+#define LRCLK_BRG 5 /* LRCLK, L/R CLocK for the A/D & D/A */
+ /* 0 == BRG1 (used for SMC1) */
+ /* 1 == BRG2 (used for SMC2) */
+ /* 2 == BRG3 (used for SCC1) */
+ /* 3 == BRG4 (MCLK) */
+ /* 4 == BRG5 */
+ /* 5 == BRG6 (LRCLK) */
+ /* 6 == BRG7 */
+ /* 7 == BRG8 (SCLK) */
+
+#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */
+#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
+ /* LRCLK = SCLK / SCLK_DIVISOR */
+
+#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */
+#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */
+ /* The 8260 (Mask B.3) seems to have */
+ /* problems generating SCLK from MCLK */
+ /* via CLK9. */
+#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */
+ /* The 8260 (Mask B.3) seems to have */
+ /* problems generating LRCLK from SCLK */
+
+#define CPM_CLK (gd->bd->bi_cpmfreq)
+#define DFBRG 4
+#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG)
+ /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
+ /* BRG = CPM * 2 / 4 */
+ /* BRG = CPM / 2 */
+
+#define CPM_BRG_EXTC_MASK ((uint)0x0000C000)
+#define CPM_BRG_EXTC_SHIFT 14
+
+#define CPM_BRG_DIV16_MASK ((uint)0x00000001)
+#define CPM_BRG_DIV16_SHIFT 1
+
+#define CPM_BRG_EXTC_BRGCLK 0
+#define CPM_BRG_EXTC_CLK3 1
+#define CPM_BRG_EXTC_CLK9 CPM_BRG_EXTC_CLK3
+#define CPM_BRG_EXTC_CLK5 2
+#define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5
+
+/*
+ * External declarations
+ */
+
+extern int Daq64xSampling;
+
+extern void Daq_BRG_Reset(uint brg);
+extern void Daq_BRG_Run(uint brg);
+
+extern void Daq_BRG_Disable(uint brg);
+extern void Daq_BRG_Enable(uint brg);
+
+extern uint Daq_BRG_Get_Div16(uint brg);
+extern void Daq_BRG_Set_Div16(uint brg, uint div16);
+
+extern uint Daq_BRG_Get_Count(uint brg);
+extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
+
+extern uint Daq_BRG_Get_ExtClk(uint brg);
+extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
+extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
+
+extern uint Daq_BRG_Rate(uint brg);
+
+extern uint Daq_Get_SampleRate(void);
+extern uint Daq_Set_SampleRate(uint rate, uint force);
+
+extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
+extern void Daq_Stop_Clocks(void);
+extern void Daq_Start_Clocks(int sample_rate);
+extern void Daq_Display_Clocks(void);
--- /dev/null
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# 82xx boards
+#
+
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <configs/sacsng.h>
+
+
+#undef DEBUG
+
+#ifndef CFG_ENV_ADDR
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+#ifndef CFG_ENV_SIZE
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+#endif
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_short *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ size_b0 = flash_get_size((vu_short *)CFG_FLASH0_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ size_b1 = flash_get_size((vu_short *)CFG_FLASH1_BASE, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+ &flash_info[0]);
+#endif
+
+ if (size_b1) {
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[1]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+ &flash_info[1]);
+#endif
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+
+ /*
+ * We only report the primary flash for PPCBoot's use.
+ */
+ return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_short *addr, flash_info_t *info)
+{
+ short i;
+ ushort value;
+ ulong base = (ulong)addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x0555] = 0xAAAA;
+ addr[0x02AA] = 0x5555;
+ addr[0x0555] = 0x9090;
+ __asm__ __volatile__(" sync\n ");
+
+ value = addr[0];
+#ifdef DEBUG
+ printf("Flash manufacturer 0x%04X\n", value);
+#endif
+
+ if(value == (ushort)AMD_MANUFACT) {
+ info->flash_id = FLASH_MAN_AMD;
+ } else if (value == (ushort)FUJ_MANUFACT) {
+ info->flash_id = FLASH_MAN_FUJ;
+ } else {
+#ifdef DEBUG
+ printf("Unknown flash manufacturer 0x%04X\n", value);
+#endif
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1]; /* device ID */
+#ifdef DEBUG
+ printf("Flash type 0x%04X\n", value);
+#endif
+
+ if(value == (ushort)AMD_ID_LV400T) {
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000; /* => 0.5 MB */
+ } else if(value == (ushort)AMD_ID_LV400B) {
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000; /* => 0.5 MB */
+ } else if(value == (ushort)AMD_ID_LV800T) {
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000; /* => 1 MB */
+ } else if(value == (ushort)AMD_ID_LV800B) {
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000; /* => 1 MB */
+ } else if(value == (ushort)AMD_ID_LV160T) {
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000; /* => 2 MB */
+ } else if(value == (ushort)AMD_ID_LV160B) {
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000; /* => 2 MB */
+ } else if(value == (ushort)AMD_ID_LV320T) {
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00400000; /* => 4 MB */
+ } else if(value == (ushort)AMD_ID_LV320B) {
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00400000; /* => 4 MB */
+ } else {
+#ifdef DEBUG
+ printf("Unknown flash type 0x%04X\n", value);
+ info->size = CFG_FLASH_SIZE;
+#else
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+#endif
+ }
+
+ /* set up sector start address table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + ((i - 3) * 0x00010000);
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + (i * 0x00010000);
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr = (volatile unsigned short *)(info->start[i]);
+ info->protect[i] = addr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (volatile unsigned short *)info->start[0];
+
+ }
+
+ addr[0] = 0xF0F0; /* reset bank */
+ __asm__ __volatile__(" sync\n ");
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ vu_short *addr = (vu_short*)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0xAAAA;
+ addr[0x02AA] = 0x5555;
+ addr[0x0555] = 0x8080;
+ addr[0x0555] = 0xAAAA;
+ addr[0x02AA] = 0x5555;
+ __asm__ __volatile__(" sync\n ");
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_short*)(info->start[sect]);
+ addr[0] = 0x3030;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (vu_short*)(info->start[l_sect]);
+ while ((addr[0] & 0x0080) != 0x0080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ addr[0] = 0xF0F0; /* reset bank */
+ __asm__ __volatile__(" sync\n ");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (vu_short*)info->start[0];
+ addr[0] = 0xF0F0; /* reset bank */
+ __asm__ __volatile__(" sync\n ");
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_short *addr = (vu_short*)(info->start[0]);
+ ulong start;
+ int flag;
+ int j;
+
+ /* Check if Flash is (sufficiently) erased */
+ if (((*(vu_long *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* The original routine was designed to write 32 bit words to
+ * 32 bit wide memory. We have 16 bit wide memory so we do
+ * two writes. We write the LSB first at dest+2 and then the
+ * MSB at dest (lousy big endian).
+ */
+ dest += 2;
+ for(j = 0; j < 2; j++) {
+ addr[0x0555] = 0xAAAA;
+ addr[0x02AA] = 0x5555;
+ addr[0x0555] = 0xA0A0;
+ __asm__ __volatile__(" sync\n ");
+
+ *((vu_short *)dest) = (ushort)data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while (*(vu_short *)dest != (ushort)data) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ dest -= 2;
+ data >>= 16;
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * I/O Port configuration table
+ *
+ * If conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#ifdef SKIP
+#undef SKIP
+#endif
+
+#ifdef CONF
+#undef CONF
+#endif
+
+#ifdef DIN
+#undef DIN
+#endif
+
+#ifdef DOUT
+#undef DOUT
+#endif
+
+#ifdef GPIO
+#undef GPIO
+#endif
+
+#ifdef SPEC
+#undef SPEC
+#endif
+
+#ifdef ACTV
+#undef ACTV
+#endif
+
+#ifdef OPEN
+#undef OPEN
+#endif
+
+#define SKIP 0 /* SKIP over this port */
+#define CONF 1 /* CONFiguration the port */
+
+#define DIN 0 /* PDIRx 0: Direction IN */
+#define DOUT 1 /* PDIRx 1: Direction OUT */
+
+#define GPIO 0 /* PPARx 0: General Purpose I/O */
+#define SPEC 1 /* PPARx 1: dedicated to a peripheral function, */
+ /* i.e. the port has a SPECial use. */
+
+#define ACTV 0 /* PODRx 0: ACTiVely driven as an output */
+#define OPEN 1 /* PODRx 1: OPEN-drain driver */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS8* */
+ /* PA30 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS7* */
+ /* PA29 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS6* */
+ /* PA28 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS5* */
+ /* PA27 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS4* */
+ /* PA26 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS3* */
+ /* PA25 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS2* */
+ /* PA24 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS1* */
+ /* PA23 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* ODIS_EN* */
+ /* PA22 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED2_EN* */
+ /* PA21 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED1_EN* */
+ /* PA20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED3_EN* */
+ /* PA19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED2_EN* */
+ /* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */
+ /* PA17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PA16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* DAC_RST* */
+ /* PA15 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH34SDATA_PU */
+ /* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */
+ /* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */
+ /* PA12 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4ACDC* */
+ /* PA11 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4TEDS* */
+ /* PA10 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4XTDS* */
+ /* PA9 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3ACDC* */
+ /* PA8 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3TEDS* */
+ /* PA7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3XTDS* */
+ /* PA6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2ACDC* */
+ /* PA5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2TEDS* */
+ /* PA4 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2XTDS* */
+ /* PA3 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PA2 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1ACDC* */
+ /* PA1 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1TEDS* */
+ /* PA0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 } /* MTRX_1XTDS* */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TX_ER */
+ /* PB30 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_DV */
+ /* PB29 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* FCC2 MII_TX_EN */
+ /* PB28 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_ER */
+ /* PB27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_COL */
+ /* PB26 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_CRS */
+ /* PB25 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD3 */
+ /* PB24 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD2 */
+ /* PB23 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD1 */
+ /* PB22 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD0 */
+ /* PB21 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD0 */
+ /* PB20 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD1 */
+ /* PB19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD2 */
+ /* PB18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD3 */
+ /* PB17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PB16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PB15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PB14 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDC1, BSDATA_ADC12 */
+ /* PB13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PB12 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCC1, LRCLK */
+ /* PB11 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1TXDD1, RSDATA_DAC12 */
+ /* PB10 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDD1, BSDATA_ADC34 */
+ /* PB9 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PB8 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCD1, LRCLK */
+ /* PB7 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PB6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* XCITE_SHDN */
+ /* PB5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* TRIGGER */
+ /* PB4 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* ARM */
+ /* PB3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
+ /* PB2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
+ /* PB1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
+ /* PB0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC30 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC29 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK3, MCLK */
+ /* PC28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* TOUT2* */
+#ifdef QQQ
+ /* PC28 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TOUT2* */
+#endif
+ /* PC27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK5, SCLK */
+ /* PC26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC25 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK7, SCLK */
+ /* PC24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC23 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK9, MCLK */
+ /* PC22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC21 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO6 (LRCLK) */
+ /* PC20 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK13, MII_RXCLK */
+ /* PC18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK14, MII_TXCLK */
+ /* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */
+ /* PC16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC15 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC2_TX */
+ /* PC14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB3 */
+ /* PC11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* TDM_STRB4 */
+ /* PC9 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN3 */
+ /* PC8 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN2 */
+ /* PC7 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN1 */
+ /* PC6 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PC5 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN2* */
+ /* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */
+ /* PC3 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* MUSH_STAT */
+ /* PC2 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* OUTDRV_STAT */
+ /* PC1 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* PHY_MDIO */
+ /* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SCC1_RX */
+ /* PD30 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SCC1_TX */
+ /* PD29 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD27 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD25 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD23 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD21 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_ADC_CS* */
+ /* PD19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_DAC_CS* */
+#if defined(CONFIG_SOFT_SPI)
+ /* PD18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_CLK */
+ /* PD17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_MOSI */
+ /* PD16 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* SPI_MISO */
+#else
+ /* PD18 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_CLK */
+ /* PD17 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_MOSI */
+ /* PD16 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* SPI_MISO */
+#endif
+#if defined(CONFIG_SOFT_I2C)
+ /* PD15 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* I2C_SDA */
+ /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* I2C_SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+ /* PD15 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SDA */
+ /* PD14 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SCL */
+#else /* normal I/O port pins */
+ /* PD15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SDA */
+ /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SCL */
+#endif
+#endif
+ /* PD13 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB1 */
+ /* PD12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB2 */
+ /* PD11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
+ /* PD10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* BRGO4 (MCLK) */
+ /* PD9 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC1_TX */
+ /* PD8 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SMC1_RX */
+ /* PD7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
+ /* PD6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
+ /* PD5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
+ /* PD4 */ { CONF, SPEC, 1, DOUT, ACTV, 1 }, /* SMC2_RX */
+ /* PD3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
+ /* PD2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
+ /* PD1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
+ /* PD0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */
+ }
+};
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8260/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Gerald Van Baren <vanbaren@cideas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/ppcboot.h>
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+//NO// #include <memtest.h>
+#include <i2c.h>
+#include <spi.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#include <status_led.h>
+#endif
+
+#include "clkinit.h"
+#include "ioconfig.h" /* I/O configuration table */
+
+/*
+ * PBI Page Based Interleaving
+ * PSDMR_PBI page based interleaving
+ * 0 bank based interleaving
+ * External Address Multiplexing (EAMUX) adds a clock to address cycles
+ * (this can help with marginal board layouts)
+ * PSDMR_EAMUX adds a clock
+ * 0 no extra clock
+ * Buffer Command (BUFCMD) adds a clock to command cycles.
+ * PSDMR_BUFCMD adds a clock
+ * 0 no extra clock
+ */
+#define CONFIG_PBI PSDMR_PBI
+#define PESSIMISTIC_SDRAM 0
+#define EAMUX 0 /* EST requires EAMUX */
+#define BUFCMD 0
+
+/*
+ * ADC/DAC Defines:
+ */
+#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */
+#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */
+#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */
+#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */
+#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */
+
+/*
+ * ADC Defines:
+ */
+#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */
+#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */
+
+#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */
+#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */
+
+#define ADC_VREF_CAP 100 /* VREF capacitor in uF */
+#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
+#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */
+#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
+ /* Wait at least 4100 LRCLK's */
+
+#define ADC_REG1_FRAME_START 0x80 /* Frame start */
+#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */
+#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */
+#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */
+
+#define ADC_REG2_128x 0x80 /* Oversample at 128x */
+#define ADC_REG2_CAL 0x40 /* System calibration enable */
+#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */
+#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */
+#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */
+#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */
+#define ADC_REG2_DFS 0x02 /* Digital format select */
+#define ADC_REG2_MUTE 0x01 /* Mute */
+
+#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */
+#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */
+#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */
+#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */
+#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */
+#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */
+#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */
+
+/*
+ * DAC Defines:
+ */
+
+#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */
+
+#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */
+#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */
+#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */
+
+#define DAC_REG1_AMUTE 0x80 /* Auto-mute */
+
+#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */
+#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */
+#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */
+#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */
+#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */
+#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */
+
+#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */
+#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */
+#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */
+#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */
+
+#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */
+#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */
+#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */
+#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */
+
+#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */
+#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */
+#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */
+#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */
+#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */
+#define DAC_REG5_FREEZE 0x04 /* Freeze */
+#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */
+#define DAC_REG5_RESERVED 0x01 /* Reserved */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+ printf ("SACSng\n");
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram(int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ volatile uchar c = 0;
+ volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
+ uint psdmr = CFG_PSDMR;
+ int i;
+ uint psrt = 14; /* for no SPD */
+ uint chipselects = 1; /* for no SPD */
+ uint sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
+ uint or = CFG_OR2_PRELIM; /* for no SPD */
+#ifdef SDRAM_SPD_ADDR
+ uint data_width;
+ uint rows;
+ uint banks;
+ uint cols;
+ uint caslatency;
+ uint width;
+ uint rowst;
+ uint sdam;
+ uint bsma;
+ uint sda10;
+ u_char spd_size;
+ u_char data;
+ u_char cksum;
+ int j;
+#endif
+
+#ifdef SDRAM_SPD_ADDR
+ /* Keep the compiler from complaining about potentially uninitialized vars */
+ data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
+
+ /*
+ * Read the SDRAM SPD EEPROM via I2C.
+ */
+ i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
+ spd_size = data;
+ cksum = data;
+ for(j = 1; j < 64; j++) { /* read only the checksummed bytes */
+ /* note: the I2C address autoincrements when alen == 0 */
+ i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
+ if(j == 5) chipselects = data & 0x0F;
+ else if(j == 6) data_width = data;
+ else if(j == 7) data_width |= data << 8;
+ else if(j == 3) rows = data & 0x0F;
+ else if(j == 4) cols = data & 0x0F;
+ else if(j == 12) {
+ /*
+ * Refresh rate: this assumes the prescaler is set to
+ * approximately 1uSec per tick.
+ */
+ switch(data & 0x7F) {
+ default:
+ case 0: psrt = 14 ; /* 15.625uS */ break;
+ case 1: psrt = 2; /* 3.9uS */ break;
+ case 2: psrt = 6; /* 7.8uS */ break;
+ case 3: psrt = 29; /* 31.3uS */ break;
+ case 4: psrt = 60; /* 62.5uS */ break;
+ case 5: psrt = 120; /* 125uS */ break;
+ }
+ }
+ else if(j == 17) banks = data;
+ else if(j == 18) {
+ caslatency = 3; /* default CL */
+#if(PESSIMISTIC_SDRAM)
+ if((data & 0x04) != 0) caslatency = 3;
+ else if((data & 0x02) != 0) caslatency = 2;
+ else if((data & 0x01) != 0) caslatency = 1;
+#else
+ if((data & 0x01) != 0) caslatency = 1;
+ else if((data & 0x02) != 0) caslatency = 2;
+ else if((data & 0x04) != 0) caslatency = 3;
+#endif
+ else {
+ printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
+ data);
+ }
+ }
+ else if(j == 63) {
+ if(data != cksum) {
+ printf ("WARNING: Configuration data checksum failure:"
+ " is 0x%02x, calculated 0x%02x\n",
+ data, cksum);
+ }
+ }
+ cksum += data;
+ }
+
+ /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
+ if(caslatency < 2) {
+ printf("CL was %d, forcing to 2\n", caslatency);
+ caslatency = 2;
+ }
+ if(rows > 14) {
+ printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
+ rows = 14;
+ }
+ if(cols > 11) {
+ printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
+ cols = 11;
+ }
+
+ if((data_width != 64) && (data_width != 72))
+ {
+ printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
+ data_width);
+ }
+ width = 3; /* 2^3 = 8 bytes = 64 bits wide */
+ /*
+ * Convert banks into log2(banks)
+ */
+ if (banks == 2) banks = 1;
+ else if(banks == 4) banks = 2;
+ else if(banks == 8) banks = 3;
+
+ sdram_size = 1 << (rows + cols + banks + width);
+
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ rowst = ((32 - 6) - (rows + cols + width)) * 2;
+#else
+ rowst = 32 - (rows + banks + cols + width);
+#endif
+
+ or = ~(sdram_size - 1) | /* SDAM address mask */
+ ((banks-1) << 13) | /* banks per device */
+ (rowst << 9) | /* rowst */
+ ((rows - 9) << 6); /* numr */
+
+ memctl->memc_or2 = or;
+
+ /*
+ * SDAM specifies the number of columns that are multiplexed
+ * (reference AN2165/D), defined to be (columns - 6) for page
+ * interleave, (columns - 8) for bank interleave.
+ *
+ * BSMA is 14 - max(rows, cols). The bank select lines come
+ * into play above the highest "address" line going into the
+ * the SDRAM.
+ */
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ sdam = cols - 8;
+ bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+ sda10 = sdam + 2;
+#else
+ sdam = cols - 6;
+ bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+ sda10 = sdam;
+#endif
+#if(PESSIMISTIC_SDRAM)
+ psdmr = (CONFIG_PBI |\
+ PSDMR_RFEN |\
+ PSDMR_RFRC_16_CLK |\
+ PSDMR_PRETOACT_8W |\
+ PSDMR_ACTTORW_8W |\
+ PSDMR_WRC_4C |\
+ PSDMR_EAMUX |\
+ PSDMR_BUFCMD) |\
+ caslatency |\
+ ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
+ (sdam << 24) |\
+ (bsma << 21) |\
+ (sda10 << 18);
+#else
+ psdmr = (CONFIG_PBI |\
+ PSDMR_RFEN |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
+ PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
+ PSDMR_WRC_1C | /* 1 clock + 7nSec */
+ EAMUX |\
+ BUFCMD) |\
+ caslatency |\
+ ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
+ (sdam << 24) |\
+ (bsma << 21) |\
+ (sda10 << 18);
+#endif
+#endif
+
+ /*
+ * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+ *
+ * "At system reset, initialization software must set up the
+ * programmable parameters in the memory controller banks registers
+ * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+ * system software should execute the following initialization sequence
+ * for each SDRAM device.
+ *
+ * 1. Issue a PRECHARGE-ALL-BANKS command
+ * 2. Issue eight CBR REFRESH commands
+ * 3. Issue a MODE-SET command to initialize the mode register
+ *
+ * Quote from Micron MT48LC8M16A2 data sheet:
+ *
+ * "...the SDRAM requires a 100uS delay prior to issuing any
+ * command other than a COMMAND INHIBIT or NOP. Starting at some
+ * point during this 100uS period and continuing at least through
+ * the end of this period, COMMAND INHIBIT or NOP commands should
+ * be applied."
+ *
+ * "Once the 100uS delay has been satisfied with at least one COMMAND
+ * INHIBIT or NOP command having been applied, a /PRECHARGE command/
+ * should be applied. All banks must then be precharged, thereby
+ * placing the device in the all banks idle state."
+ *
+ * "Once in the idle state, /two/ AUTO REFRESH cycles must be
+ * performed. After the AUTO REFRESH cycles are complete, the
+ * SDRAM is ready for mode register programming."
+ *
+ * (/emphasis/ mine, gvb)
+ *
+ * The way I interpret this, Micron start up sequence is:
+ * 1. Issue a PRECHARGE-BANK command (initial precharge)
+ * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
+ * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
+ * 4. Issue a MODE-SET command to initialize the mode register
+ *
+ * --------
+ *
+ * The initial commands are executed by setting P/LSDMR[OP] and
+ * accessing the SDRAM with a single-byte transaction."
+ *
+ * The appropriate BRx/ORx registers have already been set when we
+ * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ */
+
+ memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_psrt = psrt;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *ramaddr = c;
+
+ /*
+ * Do it a second time for the second set of chips if the DIMM has
+ * two chip selects (double sided).
+ */
+ if(chipselects > 1) {
+ ramaddr += sdram_size;
+
+ memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
+ memctl->memc_or3 = or;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *ramaddr = c;
+ }
+
+ /* return total ram size */
+ return (sdram_size * chipselects);
+}
+
+/*-----------------------------------------------------------------------
+ * Board Control Functions
+ */
+void board_poweroff (void)
+{
+ while (1); /* hang forever */
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r(void)
+{
+ /*
+ * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
+ */
+ volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
+ volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+
+ int reg; /* I2C register value */
+ char *ep; /* Environment pointer */
+ char str_buf[12] ; /* sprintf output buffer */
+ int sample_rate; /* ADC/DAC sample rate */
+ int sample_64x; /* Use 64/4 clocking for the ADC/DAC */
+ int sample_128x; /* Use 128/4 clocking for the ADC/DAC */
+ int right_just; /* Is the data to the DAC right justified? */
+ int mclk_divide; /* MCLK Divide */
+
+ /*
+ * SACSng custom initialization:
+ * Start the ADC and DAC clocks, since the Crystal parts do not
+ * work on the I2C bus until the clocks are running.
+ */
+
+ sample_rate = INITIAL_SAMPLE_RATE;
+ if ((ep = getenv("DaqSampleRate")) != NULL) {
+ sample_rate = simple_strtol(ep, NULL, 10);
+ }
+
+ sample_64x = INITIAL_SAMPLE_64X;
+ sample_128x = INITIAL_SAMPLE_128X;
+ if ((ep = getenv("Daq64xSampling")) != NULL) {
+ sample_64x = simple_strtol(ep, NULL, 10);
+ if (sample_64x) {
+ sample_128x = 0;
+ }
+ else {
+ sample_128x = 1;
+ }
+ }
+ else {
+ if ((ep = getenv("Daq128xSampling")) != NULL) {
+ sample_128x = simple_strtol(ep, NULL, 10);
+ if (sample_128x) {
+ sample_64x = 0;
+ }
+ else {
+ sample_64x = 1;
+ }
+ }
+ }
+
+ Daq_Init_Clocks(sample_rate, sample_64x);
+ sample_rate = Daq_Get_SampleRate();
+ Daq_Start_Clocks(sample_rate);
+
+ sprintf(str_buf, "%d", sample_rate);
+ setenv("DaqSampleRate", str_buf);
+
+ if (sample_64x) {
+ setenv("Daq64xSampling", "1");
+ setenv("Daq128xSampling", NULL);
+ }
+ else {
+ setenv("Daq64xSampling", NULL);
+ setenv("Daq128xSampling", "1");
+ }
+
+ /* Display the ADC/DAC clocking information */
+ Daq_Display_Clocks();
+
+ /*
+ * Determine the DAC data justification
+ */
+
+ right_just = INITIAL_RIGHT_JUST;
+ if ((ep = getenv("DaqDACRightJustified")) != NULL) {
+ right_just = simple_strtol(ep, NULL, 10);
+ }
+
+ sprintf(str_buf, "%d", right_just);
+ setenv("DaqDACRightJustified", str_buf);
+
+ /*
+ * Determine the DAC MCLK Divide
+ */
+
+ mclk_divide = INITIAL_MCLK_DIVIDE;
+ if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
+ mclk_divide = simple_strtol(ep, NULL, 10);
+ }
+
+ sprintf(str_buf, "%d", mclk_divide);
+ setenv("DaqDACMClockDivide", str_buf);
+
+ /*
+ * Initializing the I2C address in the Crystal A/Ds:
+ *
+ * 1) Wait for VREF cap to settle (10uSec per uF)
+ * 2) Release pullup on SDATA
+ * 3) Write the I2C address to register 6
+ * 4) Enable address matching by setting the MSB in register 7
+ */
+
+ printf("Initializing the ADC...\n");
+ udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
+
+ iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
+ udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
+
+ i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */
+ ADC_REG7_ADDR_ENABLE);
+
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
+ (sample_64x ? 0 : ADC_REG2_128x) |
+ ADC_REG2_HIGH_PASS_DIS |
+ ADC_REG2_SLAVE_MODE);
+
+ reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
+ if(reg != I2C_ADC_1_ADDR)
+ printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
+ reg, I2C_ADC_1_ADDR);
+
+ iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
+ udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
+
+ i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */
+
+ i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
+ (sample_64x ? 0 : ADC_REG2_128x) |
+ ADC_REG2_HIGH_PASS_DIS |
+ ADC_REG2_SLAVE_MODE);
+
+ reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
+ if(reg != I2C_ADC_2_ADDR)
+ printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
+ reg, I2C_ADC_2_ADDR);
+
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
+ ADC_REG1_FRAME_START |
+ ADC_REG1_GROUND_CAL);
+
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
+ (sample_64x ? 0 : ADC_REG2_128x) |
+ ADC_REG2_CAL |
+ ADC_REG2_HIGH_PASS_DIS |
+ ADC_REG2_SLAVE_MODE);
+
+ udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
+
+ /*
+ * Now that we have synchronized the ADC's, enable address
+ * selection on the second ADC as well as the first.
+ */
+ i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
+
+ /*
+ * Initialize the Crystal DAC
+ *
+ * Two of the config lines are used for I2C so we have to set them
+ * to the proper initialization state without inadvertantly
+ * sending an I2C "start" sequence. When we bring the I2C back to
+ * the normal state, we send an I2C "stop" sequence.
+ */
+ printf("Initializing the DAC...\n");
+
+ /*
+ * Bring the I2C clock and data lines low for initialization
+ */
+ I2C_SCL(0);
+ I2C_DELAY;
+ I2C_SDA(0);
+ I2C_ACTIVE;
+ I2C_DELAY;
+
+ /* Reset the DAC */
+ iopa->pdat &= ~DAC_RST_MASK;
+ udelay(DAC_RESET_DELAY);
+
+ /* Release the DAC reset */
+ iopa->pdat |= DAC_RST_MASK;
+ udelay(DAC_INITIAL_DELAY);
+
+ /*
+ * Cause the DAC to:
+ * Enable control port (I2C mode)
+ * Going into power down
+ */
+ i2c_reg_write(I2C_DAC_ADDR, 0x05,
+ DAC_REG5_I2C_MODE |
+ DAC_REG5_POWER_DOWN);
+
+ /*
+ * Cause the DAC to:
+ * Enable control port (I2C mode)
+ * Going into power down
+ * . MCLK divide by 1
+ * . MCLK divide by 2
+ */
+ i2c_reg_write(I2C_DAC_ADDR, 0x05,
+ DAC_REG5_I2C_MODE |
+ DAC_REG5_POWER_DOWN |
+ (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+ /*
+ * Cause the DAC to:
+ * Auto-mute disabled
+ * . Format 0, left justified 24 bits
+ * . Format 3, right justified 24 bits
+ * No de-emphasis
+ * . Single speed mode
+ * . Double speed mode
+ */
+ i2c_reg_write(I2C_DAC_ADDR, 0x01,
+ (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
+ DAC_REG1_LEFT_JUST_24_BIT) |
+ DAC_REG1_DEM_NO |
+ (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
+
+ sprintf(str_buf, "%d",
+ sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
+ setenv("DaqDACFunctionalMode", str_buf);
+
+ /*
+ * Cause the DAC to:
+ * Enable control port (I2C mode)
+ * Remove power down
+ * . MCLK divide by 1
+ * . MCLK divide by 2
+ */
+ i2c_reg_write(I2C_DAC_ADDR, 0x05,
+ DAC_REG5_I2C_MODE |
+ (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+ /*
+ * Create a I2C stop condition:
+ * low->high on data while clock is high.
+ */
+ I2C_SCL(1);
+ I2C_DELAY;
+ I2C_SDA(1);
+ I2C_DELAY;
+ I2C_TRISTATE;
+
+ printf("\n");
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+ /*
+ * Turn off the RED fail LED now that we are up and running.
+ */
+ status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+/*
+ * Show boot status: flash the LED if something goes wrong, indicating
+ * that last thing that worked and thus, by implication, what is broken.
+ *
+ * This stores the last OK value in RAM so this will not work properly
+ * before RAM is initialized. Since it is being used for indicating
+ * boot status (i.e. after RAM is initialized), that is OK.
+ */
+static void flash_code(uchar number, uchar modulo, uchar digits)
+{
+ int j;
+
+ /*
+ * Recursively do upper digits.
+ */
+ if(digits > 1) {
+ flash_code(number / modulo, modulo, digits - 1);
+ }
+
+ number = number % modulo;
+
+ /*
+ * Zero is indicated by one long flash (dash).
+ */
+ if(number == 0) {
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+ udelay(1000000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+ udelay(200000);
+ } else {
+ /*
+ * Non-zero is indicated by short flashes, one per count.
+ */
+ for(j = 0; j < number; j++) {
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+ udelay(100000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+ udelay(200000);
+ }
+ }
+ /*
+ * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
+ */
+ udelay(700000);
+}
+
+static int last_boot_progress;
+
+void show_boot_progress (int status)
+{
+ if(status != -1) {
+ last_boot_progress = status;
+ } else {
+ /*
+ * Houston, we have a problem. Blink the last OK status which
+ * indicates where things failed.
+ */
+ status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+ flash_code(last_boot_progress, 5, 3);
+ udelay(1000000);
+ status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
+ }
+}
+#endif /* CONFIG_SHOW_BOOT_PROGRESS */
+
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_SPI)
+
+#define SPI_ADC_CS_MASK 0x00000800
+#define SPI_DAC_CS_MASK 0x00001000
+
+void spi_adc_chipsel(int cs)
+{
+ volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
+
+ if(cs)
+ iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */
+ else
+ iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */
+}
+
+void spi_dac_chipsel(int cs)
+{
+ volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
+
+ if(cs)
+ iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */
+ else
+ iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */
+}
+
+/*
+ * The SPI command uses this table of functions for controlling the SPI
+ * chip selects: it calls the appropriate function to control the SPI
+ * chip selects.
+ */
+spi_chipsel_type spi_chipsel[2] = {
+ spi_adc_chipsel,
+ spi_dac_chipsel
+};
+#endif /* CFG_CMD_SPI */
+
+#endif /* CONFIG_MISC_INIT_R */
* MA 02111-1307 USA
*/
+/* #define DEBUG */
+
#include <common.h>
ulong myflush (void);
int rc = ERR_OK;
int chip1, chip2;
+ debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last);
+
/* first look for protection bits */
if (info->flash_id == FLASH_UNKNOWN)
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
-#if 0
- printf ("Erasing sector %2d ... ", sect);
-#endif
+
+ debug ("Erasing sector %2d @ %08lX... ",
+ sect, info->start[sect]);
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
/* set up the I/O ports */
rPACON = 0x3ffff;
- rPBCON=0xaaaaaaaa;
- rPBUP=0xffff;
- /* set PECON up for UART1 */
- /*INPUT INPUT nRTS1 nCTS1 INPUT INPUT INPUT */
- /* 00, 00, 11, 11, 00, 00, 00 */
- rPECON=((3 << 6)|(3 << 8));
- /* pull up nCTS1 and nRTS1 */
- rPEUP|=((1<<3)|(1<<4));
- /*INPUT INPUT INPUT TXD[1] TXD[0] RXD[1] RXD[0] */
- /* 00, 00, 00, 10, 10, 10, 10 */
- rPFCON=((2<<0)|(2<<2)|(2<<4)|(2<<6));
- /* pull up RXD0, RXD1, TXD0, TXD1 */
- rPFUP=((1<<0)|(1<<1)|(1<<2)|(1<<3));
- rPGCON=0x0;
- rPGUP=0x0;
- rOPENCR=0x0;
+ rPBCON = 0xaaaaaaaa;
+ rPBUP = 0xffff;
+ /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */
+ /* 00, 10, 10, 10, 10, 10, 10 */
+ rPFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+ /* do not pull up RXD0, RXD1, TXD0, TXD1 */
+ rPFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+ rPGCON = 0x0;
+ rPGUP = 0x0;
+ rOPENCR= 0x0;
/* arch number of SAMSUNG-Board */
/* MACH_TYPE_SMDK2400 */
command.o console.o devices.o dlmalloc.o \
docecc.o environment.o flash.o fpga.o \
hush.o kgdb.o lists.o miiphybb.o miiphyutil.o \
- s_record.o soft_i2c.o spartan2.o \
+ s_record.o soft_i2c.o soft_spi.o cmd_spi.o spartan2.o \
usb.o usb_kbd.o usb_storage.o \
virtex2.o xilinx.o
#if (CONFIG_COMMANDS & CFG_CMD_LOADS)
static ulong load_serial (ulong offset);
static int read_record (char *buf, ulong len);
+# if (CONFIG_COMMANDS & CFG_CMD_SAVES)
+static int save_serial (ulong offset, ulong size);
+static int write_record (char *buf);
+# endif /* CFG_CMD_SAVES */
static int do_echo = 1;
-#endif
+#endif /* CFG_CMD_LOADS */
#if (CONFIG_COMMANDS & CFG_CMD_BDI)
/* Check for the console hangup (if any different from serial) */
- if (syscall_tbl[SYSCALL_GETC] != serial_getc)
- {
- if (ctrlc())
- {
+ if (syscall_tbl[SYSCALL_GETC] != serial_getc) {
+ if (ctrlc()) {
return (-1);
}
}
*p = '\0';
return (p - buf);
}
+
+#if (CONFIG_COMMANDS & CFG_CMD_SAVES)
+
+int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong offset = 0;
+ ulong size = 0;
+#ifdef CFG_LOADS_BAUD_CHANGE
+ DECLARE_GLOBAL_DATA_PTR;
+ int save_baudrate, current_baudrate;
+
+ save_baudrate = current_baudrate = gd->baudrate;
+#endif
+
+ if (argc >= 2) {
+ offset = simple_strtoul(argv[1], NULL, 16);
+ }
+#ifdef CFG_LOADS_BAUD_CHANGE
+ if (argc >= 3) {
+ size = simple_strtoul(argv[2], NULL, 16);
+ }
+ if (argc == 4) {
+ save_baudrate = (int)simple_strtoul(argv[3], NULL, 10);
+
+ /* default to current baudrate */
+ if (save_baudrate == 0)
+ save_baudrate = current_baudrate;
+ }
+#else /* ! CFG_LOADS_BAUD_CHANGE */
+ if (argc == 3) {
+ size = simple_strtoul(argv[2], NULL, 16);
+ }
+#endif /* CFG_LOADS_BAUD_CHANGE */
+
+#ifdef CFG_LOADS_BAUD_CHANGE
+ if (save_baudrate != current_baudrate) {
+ printf ("## Switch baudrate to %d bps and press ENTER ...\n",
+ save_baudrate);
+ udelay(50000);
+ gd->baudrate = save_baudrate;
+ serial_setbrg ();
+ udelay(50000);
+ for (;;) {
+ if (getc() == '\r')
+ break;
+ }
+ }
+#endif /* CFG_LOADS_BAUD_CHANGE */
+ printf ("## Ready for S-Record upload, press ENTER to proceed ...\n");
+ for (;;) {
+ if (getc() == '\r')
+ break;
+ }
+ if(save_serial (offset, size)) {
+ printf ("## S-Record upload aborted\n");
+ } else {
+ printf ("## S-Record upload complete\n");
+ }
+#ifdef CFG_LOADS_BAUD_CHANGE
+ if (save_baudrate != current_baudrate) {
+ printf ("## Switch baudrate to %d bps and press ESC ...\n",
+ (int)current_baudrate);
+ udelay (50000);
+ gd->baudrate = current_baudrate;
+ serial_setbrg ();
+ udelay (50000);
+ for (;;) {
+ if (getc() == 0x1B) /* ESC */
+ break;
+ }
+ }
+#endif
+ return 0;
+}
+
+#define SREC3_START "S0030000FC\n"
+#define SREC3_FORMAT "S3%02X%08lX%s%02X\n"
+#define SREC3_END "S70500000000FA\n"
+#define SREC_BYTES_PER_RECORD 16
+
+static int save_serial (ulong address, ulong count)
+{
+ int i, c, reclen, checksum, length;
+ char *hex = "0123456789ABCDEF";
+ char record[2*SREC_BYTES_PER_RECORD+16]; /* buffer for one S-Record */
+ char data[2*SREC_BYTES_PER_RECORD+1]; /* buffer for hex data */
+
+ reclen = 0;
+ checksum = 0;
+
+ if(write_record(SREC3_START)) /* write the header */
+ return (-1);
+ do {
+ if(count) { /* collect hex data in the buffer */
+ c = *(volatile uchar*)(address + reclen); /* get one byte */
+ checksum += c; /* accumulate checksum */
+ data[2*reclen] = hex[(c>>4)&0x0f];
+ data[2*reclen+1] = hex[c & 0x0f];
+ data[2*reclen+2] = '\0';
+ ++reclen;
+ --count;
+ }
+ if(reclen == SREC_BYTES_PER_RECORD || count == 0) {
+ /* enough data collected for one record: dump it */
+ if(reclen) { /* build & write a data record: */
+ /* address + data + checksum */
+ length = 4 + reclen + 1;
+
+ /* accumulate length bytes into checksum */
+ for(i = 0; i < 2; i++)
+ checksum += (length >> (8*i)) & 0xff;
+
+ /* accumulate address bytes into checksum: */
+ for(i = 0; i < 4; i++)
+ checksum += (address >> (8*i)) & 0xff;
+
+ /* make proper checksum byte: */
+ checksum = ~checksum & 0xff;
+
+ /* output one record: */
+ sprintf(record, SREC3_FORMAT, length, address, data, checksum);
+ if(write_record(record))
+ return (-1);
+ }
+ address += reclen; /* increment address */
+ checksum = 0;
+ reclen = 0;
+ }
+ }
+ while(count);
+ if(write_record(SREC3_END)) /* write the final record */
+ return (-1);
+ return(0);
+}
+
+static int
+write_record (char *buf)
+{
+ char c;
+
+ while((c = *buf++))
+ serial_putc(c);
+
+ /* Check for the console hangup (if any different from serial) */
+
+ if (ctrlc()) {
+ return (-1);
+ }
+ return (0);
+}
+# endif /* CFG_CMD_SAVES */
+
#endif /* CFG_CMD_LOADS */
printf("## Total Size = 0x%08x = %d Bytes\n", size, size);
sprintf(buf, "%X", size);
setenv("filesize", buf);
-
+
return offset;
}
#endif /* C2MON */
+/* ----------------------------------------------------------------------------
+ MBX board from Morotola
+ ---------------------------------------------------------------------------- */
+
+#if defined( CONFIG_MBX )
+#include <../board/mbx8xx/csr.h>
+
+/* A lot of this has been taken from the RPX code in this file it works from me.
+ I have added the voltage selection for the MBX board. */
+
+/* MBX voltage bit in control register #2 */
+#define CR2_VPP12 ((uchar)0x10)
+#define CR2_VPPVDD ((uchar)0x20)
+#define CR2_VDD5 ((uchar)0x40)
+#define CR2_VDD3 ((uchar)0x80)
+
+#define PCMCIA_BOARD_MSG "MBX860"
+
+static int voltage_set (int slot, int vcc, int vpp)
+{
+ uchar reg = 0;
+
+ PCMCIA_DEBUG ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10);
+
+ switch (vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= CR2_VDD3;
+ break;
+ case 50:
+ reg |= CR2_VDD5;
+ break;
+ default:
+ return 1;
+ }
+
+ switch (vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if (vcc == vpp) {
+ reg |= CR2_VPPVDD;
+ } else {
+ return 1;
+ }
+ break;
+ case 120:
+ reg |= CR2_VPP12;
+ break;
+ default:
+ return 1;
+ }
+
+ /* first, turn off all power */
+ MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL);
+
+ /* enable new powersettings */
+ MBX_CSR2 |= reg;
+ PCMCIA_DEBUG ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2);
+
+ return (0);
+}
+
+static int hardware_enable (int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+
+ PCMCIA_DEBUG ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n",
+ 'A' + slot);
+
+ udelay (10000);
+
+ immap = (immap_t *) CFG_IMMR;
+ sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
+
+ /* disable interrupts & DMA */
+ PCMCIA_PGCRX (_slot_) = 0;
+
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ PCMCIA_DEBUG ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX (_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX (_slot_) = reg;
+ udelay (500);
+
+ /* remove all power */
+ voltage_set (slot, 0, 0);
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay (10000);
+ PCMCIA_DEBUG ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__,
+ &(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
+
+ if (pcmp->pcmc_pipr & 0x00001800) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_);
+ reg = pcmp->pcmc_pipr;
+ PCMCIA_DEBUG ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg,
+ (reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
+ (reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
+
+ if ((reg & mask) == mask) {
+ voltage_set (_slot_, 50, 0);
+ printf (" 5.0V card found: ");
+ } else {
+ voltage_set (_slot_, 33, 0);
+ printf (" 3.3V card found: ");
+ }
+
+ PCMCIA_DEBUG ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX (_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX (_slot_) = reg;
+
+ udelay (250000); /* some cards need >150 ms to come up :-( */
+
+ PCMCIA_DEBUG ("# hardware_enable done\n");
+
+ return (0);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+static int hardware_disable (int slot)
+{
+ return 0; /* No hardware to disable */
+}
+#endif /* CFG_CMD_PCMCIA */
+#endif /* CONFIG_MBX */
/* ---------------------------------------------------------------------------- */
/* R360MPI Board */
/* ---------------------------------------------------------------------------- */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SPI Read/Write Utilities
+ */
+
+#include <common.h>
+#include <command.h>
+#include <spi.h>
+#include <cmd_spi.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI)
+
+#define MAX_SPI_BYTES 32 /* max number of bytes we can handle */
+
+/*
+ * External table of chip select functions (see the appropriate board
+ * support for the actual definition of the table).
+ */
+extern spi_chipsel_type spi_chipsel[];
+
+
+/*
+ * Values from last command.
+ */
+static int device;
+static int bitlen;
+static uchar dout[MAX_SPI_BYTES];
+static uchar din[MAX_SPI_BYTES];
+
+/*
+ * SPI read/write
+ *
+ * Syntax:
+ * spi {dev} {num_bits} {dout}
+ * {dev} is the device number for controlling chip select (see TBD)
+ * {num_bits} is the number of bits to send & receive (base 10)
+ * {dout} is a hexadecimal string of data to send
+ * The command prints out the hexadecimal string received via SPI.
+ */
+
+int do_spi (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ char *cp = 0;
+ uchar tmp;
+ int j;
+ int rcode = 0;
+
+ /*
+ * We use the last specified parameters, unless new ones are
+ * entered.
+ */
+
+ if ((flag & CMD_FLAG_REPEAT) == 0)
+ {
+ if (argc >= 2)
+ device = simple_strtoul(argv[1], NULL, 10);
+ if (argc >= 3)
+ bitlen = simple_strtoul(argv[2], NULL, 10);
+ if (argc >= 4)
+ cp = argv[3];
+ for(j = 0; *cp; j++, cp++) {
+ tmp = *cp - '0';
+ if(tmp > 9)
+ tmp -= ('A' - '0') - 10;
+ if(tmp > 15)
+ tmp -= ('a' - 'A');
+ if(tmp > 15) {
+ printf("Conversion error on %c, bailing out.\n", *cp);
+ break;
+ }
+ if((j % 2) == 0)
+ dout[j / 2] = (tmp << 4);
+ else
+ dout[j / 2] |= tmp;
+ }
+ }
+
+printf("spi_chipsel[%d] = %08X\n", device, (uint)spi_chipsel[device]);
+ if(spi_xfer(spi_chipsel[device], bitlen, dout, din) != 0) {
+ printf("Error with the SPI transaction.\n");
+ rcode = 1;
+ } else {
+ cp = din;
+ for(j = 0; j < ((bitlen + 7) / 8); j++) {
+ printf("%02X", *cp++);
+ }
+ printf("\n");
+ }
+
+ return rcode;
+}
+
+#endif /* CFG_CMD_SPI */
+
CMD_TBL_RESET
CMD_TBL_RUN
CMD_TBL_SAVEENV
+ CMD_TBL_SAVES
CMD_TBL_SCCINFO
CMD_TBL_SCSIBOOT
CMD_TBL_SCSI
static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen);
static int parse_line (char *, char *[]);
-#if (CONFIG_BOOTDELAY >= 0)
+#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
static int abortboot(int);
#endif
* returns: 0 - no key string, allow autoboot
* 1 - got key string, abort
*/
-#if (CONFIG_BOOTDELAY >= 0)
+#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
# if defined(CONFIG_AUTOBOOT_KEYED)
static __inline__ int abortboot(int bootdelay)
{
int flag;
#endif
-#ifdef CONFIG_MODEM_SUPPORT
- if (do_mdm_init)
- mdm_init(); /* wait for modem connection */
-#endif /* CONFIG_MODEM_SUPPORT */
-
-#if (CONFIG_BOOTDELAY >= 0)
+#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
char *s;
int bootdelay;
#endif
char *p;
#endif
+#ifdef CONFIG_MODEM_SUPPORT
+ if (do_mdm_init)
+ mdm_init(); /* wait for modem connection */
+#endif /* CONFIG_MODEM_SUPPORT */
+
#ifdef CFG_HUSH_PARSER
ppcboot_hush_start ();
#endif
}
#endif /* CONFIG_PREBOOT */
-#if (CONFIG_BOOTDELAY >= 0)
+#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
s = getenv ("bootdelay");
- bootdelay = s ? (int)simple_strtol(s, NULL, 10) : 0;
+ bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
#if 0
printf ("### main_loop entered:\n\n");
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * Influenced by code from:
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+
+#if defined(CONFIG_SOFT_SPI)
+
+#define DEBUG_SPI
+
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#ifdef DEBUG_SPI
+#define PRINTD(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTD(fmt,args...)
+#endif
+
+
+
+/*=====================================================================*/
+/* Public Functions */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Initialization
+ */
+void spi_init (void)
+{
+#ifdef SPI_INIT
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ SPI_INIT;
+#endif
+}
+
+
+/*-----------------------------------------------------------------------
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port. That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter. Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * If the chipsel() function is not NULL, it is called with a parameter
+ * of '1' (chip select active) at the start of the transfer and again with
+ * a parameter of '0' at the end of the transfer.
+ *
+ * If the chipsel() function _is_ NULL, it the responsibility of the
+ * caller to make the appropriate chip select active before calling
+ * spi_xfer() and making it inactive after spi_xfer() returns.
+ */
+int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uchar tmpdin = 0;
+ uchar tmpdout = 0;
+ int j;
+
+ PRINTD("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n",
+ (int)chipsel, *(uint *)dout, *(uint *)din, bitlen);
+
+ if(chipsel != NULL) {
+ (*chipsel)(1); /* select the target chip */
+ }
+
+ for(j = 0; j < bitlen; j++) {
+ /*
+ * Check if it is time to work on a new byte.
+ */
+ if((j % 8) == 0) {
+ tmpdout = *dout++;
+ if(j != 0) {
+ *din++ = tmpdin;
+ }
+ tmpdin = 0;
+ }
+ SPI_SCL(0);
+ SPI_SDA(tmpdout & 0x80);
+ SPI_DELAY;
+ SPI_SCL(1);
+ SPI_DELAY;
+ tmpdin <<= 1;
+ tmpdin |= SPI_READ;
+ tmpdout <<= 1;
+ }
+ /*
+ * If the number of bits isn't a multiple of 8, shift the last
+ * bits over to left-justify them. Then store the last byte
+ * read in.
+ */
+ if((bitlen % 8) != 0)
+ tmpdin <<= 8 - (bitlen % 8);
+ *din++ = tmpdin;
+
+ SPI_SCL(0); /* SPI wants the clock left low for idle */
+
+ if(chipsel != NULL) {
+ (*chipsel)(0); /* deselect the target chip */
+
+ }
+
+ return(0);
+}
+
+#endif /* CONFIG_SOFT_SPI */
+
set_dec (get_tbclk() / CFG_HZ);
#ifdef DEBUG
- printf("interrupt_init: enabling interrupts (msr = %08x)\n",
+ printf("interrupt_init: enabling interrupts (msr = %08lx)\n",
get_msr());
#endif
set_msr (get_msr() | MSR_EE);
#ifdef DEBUG
- printf("interrupt_init: done. (msr = %08x)\n", get_msr());
+ printf("interrupt_init: done. (msr = %08lx)\n", get_msr());
#endif
return (0);
}
START = start.o kgdb.o
OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \
- bedbug_603e.o
+ bedbug_603e.o status_led.o
all: .depend $(START) $(LIB)
else
*bp |= CPM_BRG_EXTC_CLK5_15;
}
+
+#ifdef CONFIG_POST
+
+void post_word_store (ulong a)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
+
+ *save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
+
+ return *save_addr;
+}
+
+#endif /* CONFIG_POST */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <status_led.h>
+
+/*
+ * The purpose of this code is to signal the operational status of a
+ * target which usually boots over the network; while running in
+ * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
+ * message has been received, the LED is turned off. The Linux
+ * kernel, once it is running, will start blinking the LED again,
+ * with another frequency.
+ */
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_STATUS_LED
+
+typedef struct {
+ ulong mask;
+ int state;
+ int period;
+ int cnt;
+} led_dev_t;
+
+led_dev_t led_dev[] = {
+ { STATUS_LED_BIT,
+ STATUS_LED_STATE,
+ STATUS_LED_PERIOD,
+ 0,
+ },
+#if defined(STATUS_LED_BIT1)
+ { STATUS_LED_BIT1,
+ STATUS_LED_STATE1,
+ STATUS_LED_PERIOD1,
+ 0,
+ },
+#endif
+#if defined(STATUS_LED_BIT2)
+ { STATUS_LED_BIT2,
+ STATUS_LED_STATE2,
+ STATUS_LED_PERIOD2,
+ 0,
+ },
+#endif
+};
+
+#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t))
+
+static int status_led_init_done = 0;
+
+static void status_led_init (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ int i;
+
+ for (i=0; i<MAX_LED_DEV; ++i) {
+ led_dev_t *ld = &led_dev[i];
+
+ immr->STATUS_LED_PAR &= ~(ld->mask);
+#ifdef STATUS_LED_ODR
+ immr->STATUS_LED_ODR &= ~(ld->mask);
+#endif
+#if (STATUS_LED_ACTIVE == 0)
+ if (ld->state == STATUS_LED_ON)
+ immr->STATUS_LED_DAT &= ~(ld->mask);
+ else
+ immr->STATUS_LED_DAT |= ld->mask ;
+#else
+ if (ld->state == STATUS_LED_ON)
+ immr->STATUS_LED_DAT |= ld->mask ;
+ else
+ immr->STATUS_LED_DAT &= ~(ld->mask);
+#endif
+ immr->STATUS_LED_DIR |= ld->mask ;
+ }
+
+ status_led_init_done = 1;
+}
+
+void status_led_tick (ulong timestamp)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ int i;
+
+ if (!status_led_init_done)
+ status_led_init();
+
+ for (i=0; i<MAX_LED_DEV; ++i) {
+ led_dev_t *ld = &led_dev[i];
+
+ if (ld->state != STATUS_LED_BLINKING)
+ continue;
+
+ if (++(ld->cnt) >= ld->period) {
+ immr->STATUS_LED_DAT ^= ld->mask;
+ ld->cnt -= ld->period;
+ }
+ }
+}
+
+void status_led_set (int led, int state)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ led_dev_t *ld;
+
+ if (led < 0 || led >= MAX_LED_DEV)
+ return;
+
+ if (!status_led_init_done)
+ status_led_init();
+
+ ld = &led_dev[led];
+
+ switch (state) {
+ default:
+ return;
+ case STATUS_LED_BLINKING:
+ ld->cnt = 0; /* always start with full period */
+ /* fall through */ /* always start with LED _ON_ */
+ case STATUS_LED_ON:
+#if (STATUS_LED_ACTIVE == 0)
+ immr->STATUS_LED_DAT &= ~(ld->mask);
+#else
+ immr->STATUS_LED_DAT |= ld->mask ;
+#endif
+ break;
+ case STATUS_LED_OFF:
+#if (STATUS_LED_ACTIVE == 0)
+ immr->STATUS_LED_DAT |= ld->mask ;
+#else
+ immr->STATUS_LED_DAT &= ~(ld->mask);
+#endif
+ break;
+ }
+ ld->state = state;
+}
+
+#endif /* CONFIG_STATUS_LED */
board_ether_init();
#endif
+#if defined(CONFIG_NETVIA)
+#if defined(PB_ENET_PDN)
+ immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
+ immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
+ immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
+#elif defined(PC_ENET_PDN)
+ immr->im_cpm.cp_pcpar &= ~PC_ENET_PDN;
+ immr->im_cpm.cp_pcdir |= PC_ENET_PDN;
+ immr->im_cpm.cp_pcdat |= PC_ENET_PDN;
+#endif
+#endif
+
/*
* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
*/
#include <common.h>
#include <syscall.h>
-int hello_world (bd_t *bd, int argc, char *argv[])
+int hello_world (int argc, char *argv[])
{
int i;
*/
typedef struct tid_8xx_cpmtimer_s {
- bd_t *bd; /* Pointer to Board Info data */
int cpm_vec; /* CPM Interrupt Vector for this timer */
ushort *tgcrp; /* Pointer to Timer Global Config Reg. */
ushort *tmrp; /* Pointer to Timer Mode Register */
*/
#define TID_TIMER_ID 0 /* use CPM timer 1 */
-void setPeriod (bd_t * bd, tid_8xx_cpmtimer_t *hwp, ulong interval);
+void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval);
static char *usage = "\n[q, b, e, ?] ";
-int timer (bd_t * bd, int argc, char *argv[])
+int timer (int argc, char *argv[])
{
+ DECLARE_GLOBAL_DATA_PTR;
+
cpmtimer8xx_t *cpmtimerp; /* Pointer to the CPM Timer structure */
tid_8xx_cpmtimer_t hw;
tid_8xx_cpmtimer_t *hwp = &hw;
int c;
/* Pointer to CPM Timer structure */
- cpmtimerp = &((immap_t *) bd->bi_immr_base)->im_cpmtimer;
+ cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer;
mon_printf ("TIMERS=0x%x\n", (unsigned) cpmtimerp);
- hwp->bd = bd;
-
/* Initialize pointers depending on which timer we use */
switch (TID_TIMER_ID) {
case 0:
while ((c = mon_getc()) != 'q') {
if (c == 'b') {
- setPeriod (bd, hwp, TIMER_PERIOD); /* Set period and start ticking */
+ setPeriod (hwp, TIMER_PERIOD); /* Set period and start ticking */
/* Install interrupt handler (enable timer in CIMR) */
mon_install_hdlr (hwp->cpm_vec, timer_handler, hwp);
} else if (c == '?') {
#ifdef DEBUG
- cpic8xx_t *cpm_icp = &((immap_t *) bd->bi_immr_base)->im_cpic;
- sysconf8xx_t *siup = &((immap_t *) bd->bi_immr_base)->im_siu_conf;
+ cpic8xx_t *cpm_icp = &((immap_t *) gd->bd->bi_immr_base)->im_cpic;
+ sysconf8xx_t *siup = &((immap_t *) gd->bd->bi_immr_base)->im_siu_conf;
#endif
mon_printf ("\ntgcr=0x%x, tmr=0x%x, trr=0x%x,"
* Truncate to maximum period if more than this is requested - but warn about it.
*/
-void setPeriod (bd_t * bd, tid_8xx_cpmtimer_t *hwp, ulong interval)
+void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval)
{
unsigned short prescaler;
unsigned long ticks;
/* Parameter RAM offsets from the base.
*/
+#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
#define PROFF_SCC1 ((uint)0x8000)
#define PROFF_SCC2 ((uint)0x8100)
#define PROFF_SCC3 ((uint)0x8200)
#endif /* CFG_LOADS_BAUD_CHANGE */
int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+/*
+ * SAVES always requires LOADS support, but not vice versa
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_SAVES)
+#ifdef CFG_LOADS_BAUD_CHANGE
+#define CMD_TBL_SAVES MK_CMD_TBL_ENTRY( \
+ "saves", 5, 4, 0, do_save_serial, \
+ "saves - save S-Record file over serial line\n", \
+ "[ off ] [size] [ baud ]\n" \
+ " - save S-Record file over serial line" \
+ " with offset 'off', size 'size' and baudrate 'baud'\n" \
+),
+#else /* ! CFG_LOADS_BAUD_CHANGE */
+#define CMD_TBL_SAVES MK_CMD_TBL_ENTRY( \
+ "saves", 5, 3, 0, do_save_serial, \
+ "saves - save S-Record file over serial line\n", \
+ "[ off ] [size]\n" \
+ " - save S-Record file over serial line with offset 'off' and size 'size'\n" \
+),
+#endif /* CFG_LOADS_BAUD_CHANGE */
+
+int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+#else /* ! CFG_CMD_SAVES */
+#define CMD_TBL_SAVES
+#endif /* CFG_CMD_SAVES */
+
#else /* ! CFG_CMD_LOADS */
#define CMD_TBL_LOADS
+#define CMD_TBL_SAVES
#endif /* CFG_CMD_LOADS */
#define CFG_CMD_SDRAM 0x0000004000000000 /* SDRAM DIMM SPD info printout */
#define CFG_CMD_DIAG 0x0000008000000000 /* Diagnostics */
#define CFG_CMD_FPGA 0x0000010000000000 /* FPGA configuration Support */
-#define CFG_CMD_HWFLOW 0x0000020000000000 /* RTS/CTS hw flow control */
+#define CFG_CMD_HWFLOW 0x0000020000000000 /* RTS/CTS hw flow control */
+#define CFG_CMD_SAVES 0x0000040000000000 /* save S record dump */
#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFF /* ALL commands */
CFG_CMD_PCI | \
CFG_CMD_PCMCIA | \
CFG_CMD_REGINFO | \
+ CFG_CMD_SAVES | \
CFG_CMD_SCSI | \
CFG_CMD_SDRAM | \
CFG_CMD_USB )
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SPI Functions
+ */
+#ifndef _CMD_SPI_H
+#define _CMD_SPI_H
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI)
+#define CMD_TBL_SPI MK_CMD_TBL_ENTRY( \
+ "sspi", 3, 5, 1, do_spi, \
+ "sspi - SPI utility commands\n", \
+ "\
+<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n\
+ <device> - Identifies the chip select of the device\n\
+ <bit_len> - Number of bits to send (base 10)\n\
+ <dout> - Hexadecimal string that gets sent\n" \
+),
+
+int do_spi (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+
+#else
+#define CMD_TBL_SPI
+#endif /* CFG_CMD_SPI */
+
+#endif /* _CMD_SPI_H */
# endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_TQM860L, CONFIG_TQM855L */
+#if defined(CONFIG_NETVIA)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define PROFF_ENET PROFF_SCC2
+#define CPM_CR_ENET CPM_CR_CH_SCC2
+#define SCC_ENET 1
+#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
+#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
+#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
+#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
+
+#define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
+#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
+
+#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
+#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00002f00)
+
+#endif /* CONFIG_NETVIA */
+
/*********************************************************************/
/* SCC Event register as used by Ethernet.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
+/*
+ * Changed 2002-10-01
+ * Added PCMCIA defines mostly taken from other PPCBoot boards that
+ * have PCMCIA already working. If you find any bugs, incorrect assumptions
+ * feel free to fix them yourself and submit a patch.
+ * Rod Boyce <rod_boyce@stratexnet.com.
+ */
/*
* board/config.h - configuration options, board specific
*/
*/
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
-#define CONFIG_MBX 1 /* ...on an MBX module */
+#define CONFIG_MBX 1 /* ...on an MBX module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 9600
+/* Define this to use the PCI bus */
+#undef CONFIG_USE_PCI
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
+#define CONFIG_8xx_GCLK_FREQ (50000000UL)
#if 1
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
"nfsaddrs=10.0.0.99:10.0.0.2"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_BEDBUG | CFG_CMD_ELF)
+#define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \
+ CFG_CMD_PCMCIA | CFG_CMD_IDE )
+
+#define CONFIG_DOS_PARTITION
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#define CFG_HUSH_PARSER /* Hush parse for ppcboot */
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#undef CFG_HUSH_PARSER /* Hush parse for ppcboot */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
* Physical memory map as defined by the MBX PGM
*/
#define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/
-#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */
+#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */
#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
-#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */
-#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
+#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */
+#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
#define CFG_PCIMEM_OR 0xA0000108
-#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
+#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
#define CFG_PCIBRIDGE_OR 0xFFFF0108
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
+#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
-#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
+#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
/*-----------------------------------------------------------------------
* Offset in DPMEM where we keep the VPD data
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xfe000000
#ifdef DEBUG
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#endif
-#undef CFG_MONITOR_BASE /* 0x200000 to run ppcboot from RAM */
+#undef CFG_MONITOR_BASE /* 0x200000 to run ppcboot from RAM */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
-#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | \
- SIUMCR_SEME)
+/* #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
+#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
+#define CONFIG_PCMCIA_SLOT_A 1
+
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
/*-----------------------------------------------------------------------
* Debug Entry Mode
*-----------------------------------------------------------------------
*
*/
-#define CFG_DER 0
+#define CFG_DER 0
/*
* Internal Definitions
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * PPCboot port on NetVia board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
+#define CONFIG_NETVIA 1 /* ...on a NetVia board */
+#undef CONFIG_NETVIA_PLL_CLOCK /* PLL or fixed crystal clock */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
+
+#ifdef CONFIG_NETVIA_PLL_CLOCK
+/* XXX make sure that you calculate these two correctly */
+#define CFG_GCLK_MF 1350
+#define CONFIG_8xx_GCLK_FREQ 44236800
+#else
+#define CFG_GCLK_MF 1
+#define CONFIG_8xx_GCLK_FREQ 50000000
+#endif
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootm"
+
+#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_DHCP )
+
+#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_MISC_INIT_R
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#if defined(DEBUG)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#else
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#endif
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x10000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#else /* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#endif /* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#define CFG_PLPRCR ( ((CFG_GCLK_MF-1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+#define CFG_SCCR (SCCR_TBS | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR1/2 and OR1/2 (4MByte Flash Bank x 2)
+ *
+ */
+#define FLASH0_SIZE 0x00400000 /* 4MByte */
+#define FLASH0_BASE 0xF0000000
+
+#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH0_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+#define CFG_BR1_PRELIM ((FLASH0_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
+
+#define FLASH1_SIZE 0x00400000
+#define FLASH1_BASE 0xF0400000
+
+#define CFG_OR2_PRELIM ((0xFFFFFFFFLU & ~(FLASH1_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+#define CFG_BR2_PRELIM ((FLASH1_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
+
+/*
+ * BR3 and OR3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
+
+#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
+#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+
+/*
+ * BR6 (External register)
+ * 16 bit port size - leds are at high 8 bits
+ */
+#define EXTREG_BASE 0x30000000 /* external register */
+#define EXTREG_SIZE 0x00010000 /* max 64K */
+
+#define CFG_OR6_PRELIM ((0xFFFFFFFFLU & ~(EXTREG_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_15_CLK | OR_TRLX)
+#define CFG_BR6_PRELIM ((EXTREG_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA 208
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/* Ethernet at SCC2 */
+#define CONFIG_SCC2_ENET
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * Configuration settings for the WindRiver SBC8260 board.
+ * See http://www.windriver.com/products/html/sbc8260.html
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Enable debug prints */
+#undef DEBUG /* General debug */
+#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
+
+/*****************************************************************************
+ *
+ * These settings must match the way _your_ board is set up
+ *
+ *****************************************************************************/
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN 66666600
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
+ * ------- ---------- --- --- ---- ----- ----- -----
+ * 0x1 0x5 33 100 133 Open Close Open
+ * 0x1 0x6 33 100 166 Open Open Close
+ * 0x1 0x7 33 100 200 Open Open Open
+ *
+ * 0x2 0x2 33 133 133 Close Open Close
+ * 0x2 0x3 33 133 166 Close Open Open
+ * 0x2 0x4 33 133 200 Open Close Close
+ * 0x2 0x5 33 133 233 Open Close Open
+ * 0x2 0x6 33 133 266 Open Open Close
+ *
+ * 0x5 0x5 66 133 133 Open Close Open
+ * 0x5 0x6 66 133 166 Open Open Close
+ * 0x5 0x7 66 133 200 Open Open Open
+ * 0x6 0x0 66 133 233 Close Close Close
+ * 0x6 0x1 66 133 266 Close Close Open
+ * 0x6 0x2 66 133 300 Close Open Close
+ */
+#define CFG_SBC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let PPCBOOT live at 0x00000000.
+ */
+#define CFG_SBC_BOOT_LOW 1
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CFG_FLASH0_BASE 0x40000000
+#define CFG_FLASH0_SIZE 2
+
+/* What should the base address of the secondary FLASH be and how big
+ * is it (in Mbytes)? The secondary FLASH is whichever is connected
+ * to *CS6.
+ */
+#define CFG_FLASH1_BASE 0x60000000
+#define CFG_FLASH1_SIZE 2
+
+/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
+ */
+#define CONFIG_VERY_BIG_RAM 1
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)? This will normally auto-configure via the SPD.
+*/
+#define CFG_SDRAM0_BASE 0x00000000
+#define CFG_SDRAM0_SIZE 64
+
+/*
+ * Memory map example with 64 MB DIMM:
+ *
+ * 0x0000 0000 Exception Vector code, 8k
+ * :
+ * 0x0000 1FFF
+ * 0x0000 2000 Free for Application Use
+ * :
+ * :
+ *
+ * :
+ * :
+ * 0x03F5 FF30 Monitor Stack (Growing downward)
+ * Monitor Stack Buffer (0x80)
+ * 0x03F5 FFB0 Board Info Data
+ * 0x03F6 0000 Malloc Arena
+ * : CFG_ENV_SECT_SIZE, 16k
+ * : CFG_MALLOC_LEN, 128k
+ * 0x03FC 0000 RAM Copy of Monitor Code
+ * : CFG_MONITOR_LEN, 256k
+ * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU)
+
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
+#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on neither */
+#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+
+#undef CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_ON_FCC
+#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
+
+#ifdef CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
+#endif /* CONFIG_ETHER_ON_SCC */
+
+#ifdef CONFIG_ETHER_ON_FCC
+#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+
+#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
+#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
+#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
+#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
+
+#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
+ else iop->pdat &= ~0x40000000
+
+#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
+ else iop->pdat &= ~0x80000000
+
+#define MIIDELAY udelay(50)
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * - RX clk is CLK11
+ * - TX clk is CLK12
+ */
+# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE 0
+# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
+
+/*
+ * Configure for RAM tests.
+ */
+#undef CFG_DRAM_TEST /* calls other tests in board.c */
+
+
+/*
+ * Status LED for power up status feedback.
+ */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+
+#define STATUS_LED_PAR im_ioport.iop_ppara
+#define STATUS_LED_DIR im_ioport.iop_pdira
+#define STATUS_LED_ODR im_ioport.iop_podra
+#define STATUS_LED_DAT im_ioport.iop_pdata
+
+#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
+#define STATUS_LED_PERIOD (CFG_HZ)
+#define STATUS_LED_STATE STATUS_LED_OFF
+#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
+#define STATUS_LED_PERIOD1 (CFG_HZ)
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
+#define STATUS_LED_PERIOD2 (CFG_HZ/2)
+#define STATUS_LED_STATE2 STATUS_LED_ON
+
+#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
+
+#define STATUS_LED_YELLOW 0
+#define STATUS_LED_GREEN 1
+#define STATUS_LED_RED 2
+#define STATUS_LED_BOOT 1
+
+
+/*
+ * select SPI support configuration
+ */
+#define CONFIG_SOFT_SPI /* enable SPI driver */
+
+/*
+ * Software (bit-bang) SPI driver configuration
+ */
+#ifdef CONFIG_SOFT_SPI
+
+/*
+ * Software (bit-bang) SPI driver configuration
+ */
+#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
+#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
+#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
+
+#undef SPI_INIT /* no port initialization needed */
+#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
+#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
+ else immr->im_ioport.iop_pdatd &= ~I2C_MOSI
+#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
+ else immr->im_ioport.iop_pdatd &= ~I2C_SCLK
+#define SPI_DELAY /*udelay(1)*/ /* 1/2 SPI clock duration */
+#endif /* CONFIG_SOFT_SPI */
+
+
+/*
+ * select I2C support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#ifdef CONFIG_SOFT_I2C
+#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE (iop->pdir |= 0x00010000)
+#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
+#define I2C_READ ((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
+ else iop->pdat &= ~0x00010000
+#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
+ else iop->pdat &= ~0x00020000
+#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+/* Define this to reserve an entire FLASH sector for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as ppcboot, and changing variables
+ * will erase ppcboot temporarily
+ */
+#define CFG_ENV_IN_OWN_SECT 1
+
+/* Define this to contain any number of null terminated strings that
+ * will be part of the default enviroment compiled into the boot image.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+"serverip=192.168.123.201\0" \
+"ipaddr=192.168.123.203\0" \
+"checkhostname=VR8500\0" \
+"reprog="\
+ "tftpboot 0x140000 /bdi2000/ppcboot.bin; " \
+ "protect off 60000000 6003FFFF; " \
+ "erase 60000000 6003FFFF; " \
+ "cp.b 140000 60000000 $(filesize); " \
+ "protect on 60000000 6003FFFF\0" \
+"copyenv="\
+ "protect off 60040000 6004FFFF; " \
+ "erase 60040000 6004FFFF; " \
+ "cp.b 40040000 60040000 10000; " \
+ "protect on 60040000 6004FFFF\0" \
+"copyprog="\
+ "protect off 60000000 6003FFFF; " \
+ "erase 60000000 6003FFFF; " \
+ "cp.b 40000000 60000000 40000; " \
+ "protect on 60000000 6003FFFF\0" \
+"zapenv="\
+ "protect off 40040000 4004FFFF; " \
+ "erase 40040000 4004FFFF; " \
+ "protect on 40040000 4004FFFF\0" \
+"zapotherenv="\
+ "protect off 60040000 6004FFFF; " \
+ "erase 60040000 6004FFFF; " \
+ "protect on 60040000 6004FFFF\0" \
+"root-on-initrd="\
+ "setenv bootcmd "\
+ "version\\;" \
+ "echo\\;" \
+ "bootp\\;" \
+ "setenv bootargs root=/dev/ram0 rw quiet " \
+ "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
+ "run boot-hook\\;" \
+ "bootm\0" \
+"root-on-initrd-debug="\
+ "setenv bootcmd "\
+ "version\\;" \
+ "echo\\;" \
+ "bootp\\;" \
+ "setenv bootargs root=/dev/ram0 rw debug " \
+ "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
+ "run debug-hook\\;" \
+ "run boot-hook\\;" \
+ "bootm\0" \
+"root-on-nfs="\
+ "setenv bootcmd "\
+ "version\\;" \
+ "echo\\;" \
+ "bootp\\;" \
+ "setenv bootargs root=/dev/nfs rw quiet " \
+ "nfsroot=\\$(serverip):\\$(rootpath) " \
+ "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
+ "run boot-hook\\;" \
+ "bootm\0" \
+"root-on-nfs-debug="\
+ "setenv bootcmd "\
+ "version\\;" \
+ "echo\\;" \
+ "bootp\\;" \
+ "setenv bootargs root=/dev/nfs rw debug " \
+ "nfsroot=\\$(serverip):\\$(rootpath) " \
+ "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
+ "run debug-hook\\;" \
+ "run boot-hook\\;" \
+ "bootm\0" \
+"debug-checkout="\
+ "setenv checkhostname;" \
+ "setenv ethaddr 00:09:70:00:00:01;" \
+ "bootp;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) debug " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "run debug-hook;" \
+ "run boot-hook;" \
+ "bootm\0" \
+"debug-hook="\
+ "echo ipaddr $(ipaddr);" \
+ "echo serverip $(serverip);" \
+ "echo gatewayip $(gatewayip);" \
+ "echo netmask $(netmask);" \
+ "echo hostname $(hostname)\0" \
+"ana=run adc ; run dac\0" \
+"adc=run adc-12 ; run adc-34\0" \
+"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
+"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
+"dac=echo ### DAC ; imd.b 11 81 5\0" \
+"boot-hook=run ana\0"
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE 9600
+
+/* Ethernet MAC address */
+#define CONFIG_ETHADDR 00:09:70:00:00:00
+
+/* The default Ethernet MAC address can be overwritten just once */
+#ifdef CONFIG_ETHADDR
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#endif
+
+/*
+ * Define this to do some miscellaneous board-specific initialization.
+ */
+#define CONFIG_MISC_INIT_R
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
+
+/* Be selective on what keys can delay or stop the autoboot process
+ * To stop use: " "
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define DEBUG_BOOTKEYS 0
+
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#define CONFIG_BOOT_ROOT_INITRD 0 /* Use ram disk for the root file system */
+#define CONFIG_BOOT_ROOT_NFS 1 /* Use a NFS mounted root file system */
+
+#if CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+ "version;" \
+ "echo;" \
+ "bootp;" \
+ "setenv bootargs root=/dev/ram0 rw quiet " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "run boot-hook;" \
+ "bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#if CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+ "version;" \
+ "echo;" \
+ "bootp;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) quiet " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "run boot-hook;" \
+ "bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
+
+#define CONFIG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
+
+/* Add support for a few extra bootp options like:
+ * - File size
+ * - DNS
+ */
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
+ CONFIG_BOOTP_BOOTFILESIZE | \
+ CONFIG_BOOTP_DNS)
+
+/* undef this to save memory */
+#define CFG_LONGHELP
+
+/* Monitor Command Prompt */
+#define CFG_PROMPT "=> "
+
+#undef CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* What ppcboot subsytems do you want enabled? */
+#ifdef CONFIG_ETHER_ON_FCC
+# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
+ CFG_CMD_ELF | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_I2C | \
+ CFG_CMD_SPI | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_IMMAP | \
+ CFG_CMD_MII )
+#else
+# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
+ CFG_CMD_ELF | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_I2C | \
+ CFG_CMD_SPI | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_IMMAP )
+#endif /* CONFIG_ETHER_ON_FCC */
+
+/* Where do the internal registers live? */
+#define CFG_IMMR 0xF0000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
+#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
+#define CONFIG_SACSng 1 /* munged for the SACSng */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+
+#define CFG_MAXARGS 32 /* max number of command args */
+
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR 0x400000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
+ /* the exception vector table */
+ /* to the end of the DRAM */
+ /* less monitor and malloc area */
+#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
+#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
+ + CFG_MALLOC_LEN \
+ + CFG_ENV_SECT_SIZE \
+ + CFG_STACK_USAGE )
+
+#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
+ - CFG_MEM_END_USAGE )
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_FLASH_BASE CFG_FLASH0_BASE
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
+#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CFG_SBC_BOOT_LOW)
+# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
+#else
+# define CFG_SBC_HRCW_BOOT_FLAGS (0)
+#endif /* defined(CFG_SBC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
+ ((CFG_IMMR & 0x01000000) >> 7) | \
+ ((CFG_IMMR & 0x00100000) >> 4) )
+
+#define CFG_HRCW_MASTER ( HRCW_BPS10 | \
+ HRCW_DPPC11 | \
+ CFG_SBC_HRCW_IMMR | \
+ HRCW_MMR00 | \
+ HRCW_LBPC11 | \
+ HRCW_APPC10 | \
+ HRCW_CS10PC00 | \
+ (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
+ CFG_SBC_HRCW_BOOT_FLAGS )
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ */
+#define CFG_MONITOR_BASE CFG_FLASH0_BASE
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#undef CFG_FLASH_PROTECTION /* use hardware protection */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
+
+#ifndef CFG_RAMBOOT
+# define CFG_ENV_IS_IN_FLASH 1
+
+# ifdef CFG_ENV_IN_OWN_SECT
+# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+# define CFG_ENV_SECT_SIZE 0x10000
+# else
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
+# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
+# endif /* CFG_ENV_IN_OWN_SECT */
+
+#else
+# define CFG_ENV_IS_IN_NVRAM 1
+# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+# define CFG_ENV_SIZE 0x200
+#endif /* CFG_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT (HID0_ICE |\
+ HID0_DCE |\
+ HID0_ICFI |\
+ HID0_DCI |\
+ HID0_IFEM |\
+ HID0_ABE)
+
+#define CFG_HID0_FINAL (HID0_ICE |\
+ HID0_IFEM |\
+ HID0_ABE |\
+ HID0_EMCP)
+#define CFG_HID2 0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR 0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR (BCR_ETM)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_SIUMCR (SIUMCR_DPPC11 |\
+ SIUMCR_L2CPC00 |\
+ SIUMCR_APPC10 |\
+ SIUMCR_MMR00)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#define CFG_SYPCR (SYPCR_SWTC |\
+ SYPCR_BMT |\
+ SYPCR_PBME |\
+ SYPCR_LBME |\
+ SYPCR_SWRI |\
+ SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC (TMCNTSC_SEC |\
+ TMCNTSC_ALR |\
+ TMCNTSC_TCF |\
+ TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR (PISCR_PS |\
+ PISCR_PTF |\
+ PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR 0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration 13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR 0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * Bank Bus Machine PortSz Device
+ * ---- --- ------- ------ ------
+ * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
+ * 1 60x GPCM -- bit (Unused)
+ * 2 60x SDRAM 64 bit SDRAM (DIMM)
+ * 3 60x SDRAM 64 bit SDRAM (DIMM)
+ * 4 60x GPCM -- bit (Unused)
+ * 5 60x GPCM -- bit (Unused)
+ * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
+ */
+
+/*-----------------------------------------------------------------------
+ * BR0,BR1 - Base Register
+ * Ref: Section 10.3.1 on page 10-14
+ * OR0,OR1 - Option Register
+ * Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0 - Primary FLASH
+ */
+
+/* BR0 is configured as follows:
+ *
+ * - Base address of 0x40000000
+ * - 16 bit port size
+ * - Data errors checking is disabled
+ * - Read and write access
+ * - GPCM 60x bus
+ * - Access are handled by the memory controller according to MSEL
+ * - Not used for atomic operations
+ * - No data pipelining is done
+ * - Valid
+ */
+#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
+
+/* OR0 is configured as follows:
+ *
+ * - 4 MB
+ * - *BCTL0 is asserted upon access to the current memory bank
+ * - *CW / *WE are negated a quarter of a clock earlier
+ * - *CS is output at the same time as the address lines
+ * - Uses a clock cycle length of 5
+ * - *PSDVAL is generated internally by the memory controller
+ * unless *GTA is asserted earlier externally.
+ * - Relaxed timing is generated by the GPCM for accesses
+ * initiated to this memory region.
+ * - One idle clock is inserted between a read access from the
+ * current bank and the next access.
+ */
+#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_TRLX |\
+ ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ * Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ * Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 2,3 - SDRAM DIMM
+ */
+
+/* The BR2 is configured as follows:
+ *
+ * - Base address of 0x00000000
+ * - 64 bit port size (60x bus only)
+ * - Data errors checking is disabled
+ * - Read and write access
+ * - SDRAM 60x bus
+ * - Access are handled by the memory controller according to MSEL
+ * - Not used for atomic operations
+ * - No data pipelining is done
+ * - Valid
+ */
+#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
+
+#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
+
+/* With a 64 MB DIMM, the OR2 is configured as follows:
+ *
+ * - 64 MB
+ * - 4 internal banks per device
+ * - Row start address bit is A8 with PSDMR[PBI] = 0
+ * - 12 row address lines
+ * - Back-to-back page mode
+ * - Internal bank interleaving within save device enabled
+ */
+#if (CFG_SDRAM0_SIZE == 64)
+#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A8 |\
+ ORxS_NUMR_12)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ * Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+
+/* Address that the DIMM SPD memory lives at.
+ */
+#define SDRAM_SPD_ADDR 0x50
+
+#if (CFG_SDRAM0_SIZE == 64)
+/* With a 64 MB DIMM, the PSDMR is configured as follows:
+ *
+ * - Bank Based Interleaving,
+ * - Refresh Enable,
+ * - Address Multiplexing where A5 is output on A14 pin
+ * (A6 on A15, and so on),
+ * - use address pins A14-A16 as bank select,
+ * - A9 is output on SDA10 during an ACTIVATE command,
+ * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ * is 3 clocks,
+ * - earliest timing for READ/WRITE command after ACTIVATE command is
+ * 2 clocks,
+ * - earliest timing for PRECHARGE after last data was read is 1 clock,
+ * - earliest timing for PRECHARGE after last data was written is 1 clock,
+ * - CAS Latency is 2.
+ */
+#define CFG_PSDMR (PSDMR_RFEN |\
+ PSDMR_SDAM_A14_IS_A5 |\
+ PSDMR_BSMA_A14_A16 |\
+ PSDMR_SDA10_PBI0_A9 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_3W |\
+ PSDMR_ACTTORW_2W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+/*
+ * Shoot for approximately 1MHz on the prescaler.
+ */
+#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
+#define CFG_MPTPR MPTPR_PTP_DIV64
+#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
+#define CFG_MPTPR MPTPR_PTP_DIV32
+#else
+#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
+#define CFG_MPTPR MPTPR_PTP_DIV32
+#endif
+#define CFG_PSRT 14
+
+
+/*-----------------------------------------------------------------------
+ * BR6 - Base Register
+ * Ref: Section 10.3.1 on page 10-14
+ * OR6 - Option Register
+ * Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 6 - Secondary FLASH
+ *
+ * The secondary FLASH is connected to *CS6
+ */
+#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
+
+/* BR6 is configured as follows:
+ *
+ * - Base address of 0x60000000
+ * - 16 bit port size
+ * - Data errors checking is disabled
+ * - Read and write access
+ * - GPCM 60x bus
+ * - Access are handled by the memory controller according to MSEL
+ * - Not used for atomic operations
+ * - No data pipelining is done
+ * - Valid
+ */
+# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
+
+/* OR6 is configured as follows:
+ *
+ * - 2 MB
+ * - *BCTL0 is asserted upon access to the current memory bank
+ * - *CW / *WE are negated a quarter of a clock earlier
+ * - *CS is output at the same time as the address lines
+ * - Uses a clock cycle length of 5
+ * - *PSDVAL is generated internally by the memory controller
+ * unless *GTA is asserted earlier externally.
+ * - Relaxed timing is generated by the GPCM for accesses
+ * initiated to this memory region.
+ * - One idle clock is inserted between a read access from the
+ * current bank and the next access.
+ */
+# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_TRLX |\
+ ORxG_EHTR)
+#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.3.27
#define CONFIG_SERVERIP 192.168.3.1
-#define CONFIG_BOOTCOMMAND "tftpboot $(loadaddr) $(loadfile);" \
- "setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
- "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
- "bootm"
+#define CONFIG_BOOTCOMMAND "run flash_nfs"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "nfs_args=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "rootpath=/opt/eldk/arm_920TDI\0" \
+ "ram_args=setenv bootargs root=/dev/ram rw\0" \
+ "add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
+ "add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \
+ "load=tftp 0xC100000 /tftpboot/TRAB/ppcboot.bin\0" \
+ "update=protect off 1:0-7;era 1:0-7;cp.b 0xc100000 0 $(filesize);" \
+ "setenv filesize;saveenv\0" \
+ "loadfile=/tftpboot/TRAB/pImage\0" \
+ "loadaddr=c400000\0" \
+ "net_load=tftpboot $(loadaddr) $(loadfile)\0" \
+ "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
+ "kernel_addr=00040000\0" \
+ "flash_nfs=run nfs_args add_net add_misc;bootm $(kernel_addr)\0"
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
#define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */
#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */
+#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
/* Micron Technologies (INTEL compat.) */
#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
#define AMD_ID_F040B 0xA4 /* 29F040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
-
+#define STM_ID_M29W040B 0xE3 /* M29W040B ID */
+ /* 4 Mbit, 512K x 8, */
+ /* 8 64K x 8 uniform sectors */
#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */
#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
#define FLASH_MAN_AMD 0x00000000 /* AMD */
#define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */
#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */
+#define FLASH_MAN_MX 0x00030000 /* MXIC */
+#define FLASH_MAN_STM 0x00040000
#define FLASH_MAN_SST 0x00100000
-#define FLASH_MAN_STM 0x00200000
#define FLASH_MAN_INTEL 0x00300000
#define FLASH_MAN_MT 0x00400000
#define FLASH_MAN_SHARP 0x00500000
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPI_H_
+#define _SPI_H_
+
+/*
+ * The function call pointer type used to drive the chip select.
+ */
+typedef void (*spi_chipsel_type)(int cs);
+
+
+/*-----------------------------------------------------------------------
+ * Initialization, must be called once on start up.
+ */
+void spi_init(void);
+
+
+/*-----------------------------------------------------------------------
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port. That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter. Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * If the chipsel() function is not NULL, it is called with a parameter
+ * of '1' (chip select active) at the start of the transfer and again with
+ * a parameter of '0' at the end of the transfer.
+ *
+ * If the chipsel() function _is_ NULL, it the responsibility of the
+ * caller to make the appropriate chip select active before calling
+ * spi_xfer() and making it inactive after spi_xfer() returns.
+ *
+ * spi_xfer() interface:
+ * chipsel: Routine to call to set/clear the chip select:
+ * if chipsel is NULL, it is not used.
+ * if(cs), make the chip select active (typically '0').
+ * if(!cs), make the chip select inactive (typically '1').
+ * dout: Pointer to a string of bits to send out. The bits are
+ * held in a byte array and are sent MSB first.
+ * din: Pointer to a string of bits that will be filled in.
+ * bitlen: How many bits to write and read.
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din);
+
+#endif /* _SPI_H_ */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+/***** Someone else defines these *************************************/
+#elif defined(STATUS_LED_PAR)
+
+ /*
+ * ADVICE: Define in your board configuration file rather than
+ * filling this file up with lots of custom board stuff.
+ */
+
+/***** NetVia ********************************************************/
+#elif defined(CONFIG_NETVIA)
+
+#define STATUS_LED_PAR im_ioport.iop_pdpar
+#define STATUS_LED_DIR im_ioport.iop_pddir
+#undef STATUS_LED_ODR
+#define STATUS_LED_DAT im_ioport.iop_pddat
+
+# define STATUS_LED_BIT 0x0080 /* PD.8 */
+# define STATUS_LED_PERIOD (CFG_HZ / 2)
+# define STATUS_LED_STATE STATUS_LED_BLINKING
+
+# define STATUS_LED_BIT1 0x0040 /* PD.9 */
+# define STATUS_LED_PERIOD1 (CFG_HZ / 2)
+# define STATUS_LED_STATE1 STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
+# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
/************************************************************************/
#else
# error Status LED configuration missing
char *commandline = getenv("bootargs");
#endif
+ theKernel = (void (*)(int, int))ntohl(hdr->ih_ep);
+
/*
* Check if there is an initrd image
*/
initrd_end = 0;
}
- theKernel = (void (*)(int, int))ntohl(hdr->ih_ep);
-
#ifdef DEBUG
printf ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)theKernel);
}
+#ifndef ATAG_INITRD2
+#define ATAG_INITRD2 0x54420005
+#endif
static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
{
/* an ATAG_INITRD node tells the kernel where the compressed
* ramdisk can be found. ATAG_RDIMG is a better name, actually.
*/
- params->hdr.tag = ATAG_INITRD;
+ params->hdr.tag = ATAG_INITRD2;
params->hdr.size = tag_size(tag_initrd);
params->u.initrd.start = initrd_start;
#ifdef CONFIG_POST
#include <post.h>
+
+#if defined(CONFIG_8xx)
#include <commproc.h>
+#elif defined(CONFIG_MPC8260)
+#include <asm/cpm_8260.h>
+#else
+#error "Apparently a bad configuration, please fix."
+#endif
+
#include <command.h>
#include <net.h>
#include <common.h>
/* Memory test
+ *
+ * General observations:
+ * o The recommended test sequence is to test the data lines: if they are
+ * broken, nothing else will work properly. Then test the address
+ * lines. Finally, test the cells in the memory now that the test
+ * program knows that the address and data lines work properly.
+ * This sequence also helps isolate and identify what is faulty.
+ *
+ * o For the address line test, it is a good idea to use the base
+ * address of the lowest memory location, which causes a '1' bit to
+ * walk through a field of zeros on the address lines and the highest
+ * memory location, which causes a '0' bit to walk through a field of
+ * '1's on the address line.
+ *
+ * o Floating buses can fool memory tests if the test routine writes
+ * a value and then reads it back immediately. The problem is, the
+ * write will charge the residual capacitance on the data bus so the
+ * bus retains its state briefely. When the test program reads the
+ * value back immediately, the capacitance of the bus can allow it
+ * to read back what was written, even though the memory circuitry
+ * is broken. To avoid this, the test program should write a test
+ * pattern to the target location, write a different pattern elsewhere
+ * to charge the residual capacitance in a differnt manner, then read
+ * the target location back.
+ *
+ * o Always read the target location EXACTLY ONCE and save it in a local
+ * variable. The problem with reading the target location more than
+ * once is that the second and subsequent reads may work properly,
+ * resulting in a failed test that tells the poor technician that
+ * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
+ * doesn't help him one bit and causes puzzled phone calls. Been there,
+ * done that.
+ *
+ * Data line test:
+ * ---------------
+ * This tests data lines for shorts and opens by forcing adjacent data
+ * to opposite states. Because the data lines could be routed in an
+ * arbitrary manner the must ensure test patterns ensure that every case
+ * is tested. By using the following series of binary patterns every
+ * combination of adjacent bits is test regardless of routing.
+ *
+ * ...101010101010101010101010
+ * ...110011001100110011001100
+ * ...111100001111000011110000
+ * ...111111110000000011111111
+ *
+ * Carrying this out, gives us six hex patterns as follows:
+ *
+ * 0xaaaaaaaaaaaaaaaa
+ * 0xcccccccccccccccc
+ * 0xf0f0f0f0f0f0f0f0
+ * 0xff00ff00ff00ff00
+ * 0xffff0000ffff0000
+ * 0xffffffff00000000
+ *
+ * To test for short and opens to other signals on our boards, we
+ * simply test with the 1's complemnt of the paterns as well, resulting
+ * in twelve patterns total.
+ *
+ * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
+ * written to a different address in case the data lines are floating.
+ * Thus, if a byte lane fails, you will see part of the special
+ * pattern in that byte lane when the test runs. For example, if the
+ * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
+ * (for the 'a' test pattern).
+ *
+ * Address line test:
+ * ------------------
+ * This function performs a test to verify that all the address lines
+ * hooked up to the RAM work properly. If there is an address line
+ * fault, it usually shows up as two different locations in the address
+ * map (related by the faulty address line) mapping to one physical
+ * memory storage location. The artifact that shows up is writing to
+ * the first location "changes" the second location.
+ *
+ * To test all address lines, we start with the given base address and
+ * xor the address with a '1' bit to flip one address line. For each
+ * test, we shift the '1' bit left to test the next address line.
+ *
+ * In the actual code, we start with address sizeof(ulong) since our
+ * test pattern we use is a ulong and thus, if we tried to test lower
+ * order address bits, it wouldn't work because our pattern would
+ * overwrite itself.
+ *
+ * Example for a 4 bit address space with the base at 0000:
+ * 0000 <- base
+ * 0001 <- test 1
+ * 0010 <- test 2
+ * 0100 <- test 3
+ * 1000 <- test 4
+ * Example for a 4 bit address space with the base at 0010:
+ * 0010 <- base
+ * 0011 <- test 1
+ * 0000 <- (below the base address, skipped)
+ * 0110 <- test 2
+ * 1010 <- test 3
*
- * The memory test verifies RAM using sequential writes and reads
+ * The test locations are successively tested to make sure that they are
+ * not "mirrored" onto the base address due to a faulty address line.
+ * Note that the base and each test location are related by one address
+ * line flipped. Note that the base address need not be all zeros.
+ *
+ * Memory tests 1-4:
+ * -----------------
+ * These tests verify RAM using sequential writes and reads
* to/from RAM. There are several test cases that use different patterns to
* verify RAM. Each test case fills a region of RAM with one pattern and
* then reads the region back and compares its contents with the pattern.
#if CONFIG_POST & CFG_POST_MEMORY
+/*
+ * Define INJECT_*_ERRORS for testing error detection in the presence of
+ * _good_ hardware.
+ */
+#undef INJECT_DATA_ERRORS
+#undef INJECT_ADDRESS_ERRORS
+
+#ifdef INJECT_DATA_ERRORS
+#warning "Injecting data line errors for testing purposes"
+#endif
+
+#ifdef INJECT_ADDRESS_ERRORS
+#warning "Injecting address line errors for testing purposes"
+#endif
+
+
+/*
+ * This function performs a double word move from the data at
+ * the source pointer to the location at the destination pointer.
+ * This is helpful for testing memory on processors which have a 64 bit
+ * wide data bus.
+ *
+ * On the PowerPC, use assembly and a floating point move: this does a
+ * 64 bit move.
+ *
+ * For other processors, let the compiler generate the best code it can.
+ */
+static void move64(unsigned long long *src, unsigned long long *dest)
+{
+#ifdef CONFIG_PPC
+ asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
+ "stfd 0, 0(4)" /* *dest = fpr0 */
+ : : : "fr0" ); /* Clobbers fr0 */
+ return;
+#else
+ *dest = *src;
+#endif
+}
+
+/*
+ * This is 64 bit wide test patterns. Note that they reside in ROM
+ * (which presumably works) and the tests write them to RAM which may
+ * not work.
+ *
+ * The "otherpattern" is written to drive the data bus to values other
+ * than the test pattern. This is for detecting floating bus lines.
+ *
+ */
+const static unsigned long long pattern[] = {
+ 0xaaaaaaaaaaaaaaaa,
+ 0xcccccccccccccccc,
+ 0xf0f0f0f0f0f0f0f0,
+ 0xff00ff00ff00ff00,
+ 0xffff0000ffff0000,
+ 0xffffffff00000000,
+ 0x00000000ffffffff,
+ 0x0000ffff0000ffff,
+ 0x00ff00ff00ff00ff,
+ 0x0f0f0f0f0f0f0f0f,
+ 0x3333333333333333,
+ 0x5555555555555555};
+const unsigned long long otherpattern = 0x0123456789abcdef;
+
+
+static int memory_post_dataline(unsigned long long * pmem)
+{
+ unsigned long long temp64;
+ int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
+ int i;
+ unsigned int hi, lo, pathi, patlo;
+ int ret = 0;
+
+ for ( i = 0; i < num_patterns; i++) {
+ move64((unsigned long long *)&(pattern[i]), pmem++);
+ /*
+ * Put a different pattern on the data lines: otherwise they
+ * may float long enough to read back what we wrote.
+ */
+ move64((unsigned long long *)&otherpattern, pmem--);
+ move64(pmem, &temp64);
+
+#ifdef INJECT_DATA_ERRORS
+ temp64 ^= 0x00008000;
+#endif
+
+ if (temp64 != pattern[i]){
+ pathi = (pattern[i]>>32) & 0xffffffff;
+ patlo = pattern[i] & 0xffffffff;
+
+ hi = (temp64>>32) & 0xffffffff;
+ lo = temp64 & 0xffffffff;
+
+ post_log ("Memory (date line) error at %08x, "
+ "wrote %08x%08x, read %08x%08x !\n",
+ pmem, pathi, patlo, hi, lo);
+ ret = -1;
+ }
+ }
+ return ret;
+}
+
+static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
+{
+ ulong *target;
+ ulong *end;
+ ulong readback;
+ ulong xor;
+ int ret = 0;
+
+ end = base + size;
+ xor = 0;
+ for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
+ target = (ulong *)((ulong)testaddr ^ xor);
+ if((target >= base) && (target < end)) {
+ *testaddr = ~*target;
+ readback = *target;
+
+#ifdef INJECT_ADDRESS_ERRORS
+ if(xor == 0x00008000) {
+ readback = *testaddr;
+ }
+#endif
+ if(readback == *testaddr) {
+ post_log ("Memory (address line) error at %08x<->%08x, "
+ "XOR value %08x !\n",
+ testaddr, target, xor);
+ ret = -1;
+ }
+ }
+ }
+ return ret;
+}
+
static int memory_post_test1 (unsigned long start,
unsigned long size,
unsigned long val)
{
unsigned long i;
ulong *mem = (ulong *) start;
+ ulong readback;
int ret = 0;
for (i = 0; i < size / sizeof (ulong); i++) {
}
for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
- if (mem[i] != val) {
+ readback = mem[i];
+ if (readback != val) {
post_log ("Memory error at %08x, "
- "written %08x, read %08x !\n",
- mem + i, val, mem[i]);
+ "wrote %08x, read %08x !\n",
+ mem + i, val, readback);
ret = -1;
break;
{
unsigned long i;
ulong *mem = (ulong *) start;
+ ulong readback;
int ret = 0;
for (i = 0; i < size / sizeof (ulong); i++) {
}
for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
- if (mem[i] != (1 << (i % 32))) {
+ readback = mem[i];
+ if (readback != (1 << (i % 32))) {
post_log ("Memory error at %08x, "
- "written %08x, read %08x !\n",
- mem + i, 1 << (i % 32), mem[i]);
+ "wrote %08x, read %08x !\n",
+ mem + i, 1 << (i % 32), readback);
ret = -1;
break;
{
unsigned long i;
ulong *mem = (ulong *) start;
+ ulong readback;
int ret = 0;
for (i = 0; i < size / sizeof (ulong); i++) {
}
for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
- if (mem[i] != i) {
+ readback = mem[i];
+ if (readback != i) {
post_log ("Memory error at %08x, "
- "written %08x, read %08x !\n",
- mem + i, i, mem[i]);
+ "wrote %08x, read %08x !\n",
+ mem + i, i, readback);
ret = -1;
break;
{
unsigned long i;
ulong *mem = (ulong *) start;
+ ulong readback;
int ret = 0;
for (i = 0; i < size / sizeof (ulong); i++) {
}
for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
- if (mem[i] != ~i) {
+ readback = mem[i];
+ if (readback != ~i) {
post_log ("Memory error at %08x, "
- "written %08x, read %08x !\n",
- mem + i, ~i, mem[i]);
+ "wrote %08x, read %08x !\n",
+ mem + i, ~i, readback);
ret = -1;
break;
{
int ret = 0;
+ if (ret == 0)
+ ret = memory_post_dataline ((long long *)start);
+ WATCHDOG_RESET ();
+ if (ret == 0)
+ ret = memory_post_addrline ((long *)start, (long *)start, size);
+ WATCHDOG_RESET ();
+ if (ret == 0)
+ ret = memory_post_addrline ((long *)(start + size - 8),
+ (long *)start, size);
+ WATCHDOG_RESET ();
if (ret == 0)
ret = memory_post_test1 (start, size, 0x00000000);
WATCHDOG_RESET ();
#include <post.h>
-int cache_post_test (int flags);
-int watchdog_post_test (int flags);
-int i2c_post_test (int flags);
-int rtc_post_test (int flags);
-int memory_post_test (int flags);
-int cpu_post_test (int flags);
-int uart_post_test (int flags);
-int ether_post_test (int flags);
-int spi_post_test (int flags);
-int usb_post_test (int flags);
-int spr_post_test (int flags);
+extern int cache_post_test (int flags);
+extern int watchdog_post_test (int flags);
+extern int i2c_post_test (int flags);
+extern int rtc_post_test (int flags);
+extern int memory_post_test (int flags);
+extern int cpu_post_test (int flags);
+extern int uart_post_test (int flags);
+extern int ether_post_test (int flags);
+extern int spi_post_test (int flags);
+extern int usb_post_test (int flags);
+extern int spr_post_test (int flags);
struct post_test post_list[] =
{
#ifdef CONFIG_POST
#include <post.h>
+#if defined(CONFIG_8xx)
#include <commproc.h>
+#elif defined(CONFIG_MPC8260)
+#include <asm/cpm_8260.h>
+#else
+#error "Apparently a bad configuration, please fix."
+#endif
#include <command.h>
#include <net.h>
#ifdef CONFIG_POST
#include <post.h>
-#include <commproc.h>
-#include <command.h>
#if CONFIG_POST & CFG_POST_USB
+#include <commproc.h>
+#include <command.h>
+
#define TOUT_LOOP 100
#define PROFF_USB ((uint)0x0000)
projects / users / rw / ppcboot.git / commitdiff