aw_reg_add_dword /= sizeof(uint32_t);
 
                packets_vec[0].bitfields2.reg_offset =
-                                       aw_reg_add_dword - CONFIG_REG_BASE;
+                                       aw_reg_add_dword - AMD_CONFIG_REG_BASE;
 
                packets_vec[0].reg_data[0] = cntl.u32All;
 
                aw_reg_add_dword /= sizeof(uint32_t);
 
                packets_vec[1].bitfields2.reg_offset =
-                                       aw_reg_add_dword - CONFIG_REG_BASE;
+                                       aw_reg_add_dword - AMD_CONFIG_REG_BASE;
                packets_vec[1].reg_data[0] = addrHi.u32All;
 
                aw_reg_add_dword =
                aw_reg_add_dword /= sizeof(uint32_t);
 
                packets_vec[2].bitfields2.reg_offset =
-                               aw_reg_add_dword - CONFIG_REG_BASE;
+                               aw_reg_add_dword - AMD_CONFIG_REG_BASE;
                packets_vec[2].reg_data[0] = addrLo.u32All;
 
                /* enable watch flag if address is not zero*/
                aw_reg_add_dword /= sizeof(uint32_t);
 
                packets_vec[3].bitfields2.reg_offset =
-                                       aw_reg_add_dword - CONFIG_REG_BASE;
+                                       aw_reg_add_dword - AMD_CONFIG_REG_BASE;
                packets_vec[3].reg_data[0] = cntl.u32All;
 
                status = dbgdev_diq_submit_ib(
        packets_vec[1].header.opcode = IT_SET_CONFIG_REG;
        packets_vec[1].header.type = PM4_TYPE_3;
        packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) -
-                                               CONFIG_REG_BASE;
+                                               AMD_CONFIG_REG_BASE;
 
        packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;
        packets_vec[1].bitfields2.insert_vmid = 1;
 
 
 /* CONFIG reg space definition */
 enum {
-       CONFIG_REG_BASE = 0x2000,       /* in dwords */
-       CONFIG_REG_END = 0x2B00,
-       CONFIG_REG_SIZE = CONFIG_REG_END - CONFIG_REG_BASE
+       AMD_CONFIG_REG_BASE = 0x2000,   /* in dwords */
+       AMD_CONFIG_REG_END = 0x2B00,
+       AMD_CONFIG_REG_SIZE = AMD_CONFIG_REG_END - AMD_CONFIG_REG_BASE
 };
 
 /* SH reg space definition */