#define HSSPI_FIFO_REG(x)                      (0x200 + (x) * 0x200)
 
 
+#define HSSPI_OP_MULTIBIT                      BIT(11)
 #define HSSPI_OP_CODE_SHIFT                    13
 #define HSSPI_OP_SLEEP                         (0 << HSSPI_OP_CODE_SHIFT)
 #define HSSPI_OP_READ_WRITE                    (1 << HSSPI_OP_CODE_SHIFT)
        if (opcode != HSSPI_OP_READ)
                step_size -= HSSPI_OPCODE_LEN;
 
-       __raw_writel(0 << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
-                    2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
-                    2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
+       if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
+           (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
+               opcode |= HSSPI_OP_MULTIBIT;
+
+       __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
+                    1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
                     bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
 
        while (pending > 0) {
        master->num_chipselect = 8;
        master->setup = bcm63xx_hsspi_setup;
        master->transfer_one_message = bcm63xx_hsspi_transfer_one;
-       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
+                           SPI_RX_DUAL | SPI_TX_DUAL;
        master->bits_per_word_mask = SPI_BPW_MASK(8);
        master->auto_runtime_pm = true;