drm/i915: Move LPT PCH readout code

Nuke the hsw_get_ddi_port_state() eyesore by putting the
readout code into intel_pch_display.c, and calling it directly
from hsw_crt_get_config().

Note that the nuked TRANS_DDI_FUNC_CTL readout from
hsw_get_ddi_port_state() is now etirely redundant since we
get called from the encoder->get_config() so we already know
we're dealing with the correct DDI port. Previously the
code was called from a place where that wasn't known so
it had to checked manually.

v2: Clarify the TRANS_DDI_FUNC_CTL change (Dave)
    Nuke the now unused *TRANS_DDI_FUNC_CTL_VAL_TO_PORT() (Dave)

Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211018153525.21597-1-ville.syrjala@linux.intel.com
Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 4038ae342ea16e57901921f1fa85c09638bec026..03cfae46f92f614d2094a4d2c62e27662fbca1e7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -147,6 +147,8 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
+       lpt_pch_get_config(pipe_config);
+
        hsw_ddi_get_config(encoder, pipe_config);
 
        pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 31f51d056d55ef93963dd269fcc885052235becd..482498188c6cc6576ffaad508b17fcb22c86682f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4088,8 +4088,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
                                             &pipe_config->dp_m2_n2);
 }
 
-static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
-                                  struct intel_crtc_state *pipe_config)
+void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
+                           struct intel_crtc_state *pipe_config)
 {
        intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
                                     &pipe_config->fdi_m_n, NULL);
@@ -4484,45 +4484,6 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
        return transcoder_is_dsi(pipe_config->cpu_transcoder);
 }
 
-static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
-                                  struct intel_crtc_state *pipe_config)
-{
-       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-       enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
-       enum port port;
-       u32 tmp;
-
-       if (transcoder_is_dsi(cpu_transcoder)) {
-               port = (cpu_transcoder == TRANSCODER_DSI_A) ?
-                                               PORT_A : PORT_B;
-       } else {
-               tmp = intel_de_read(dev_priv,
-                                   TRANS_DDI_FUNC_CTL(cpu_transcoder));
-               if (!(tmp & TRANS_DDI_FUNC_ENABLE))
-                       return;
-               if (DISPLAY_VER(dev_priv) >= 12)
-                       port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
-               else
-                       port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
-       }
-
-       /*
-        * Haswell has only FDI/PCH transcoder A. It is which is connected to
-        * DDI E. So just check whether this pipe is wired to DDI E and whether
-        * the PCH transcoder is on.
-        */
-       if (DISPLAY_VER(dev_priv) < 9 &&
-           (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
-               pipe_config->has_pch_encoder = true;
-
-               tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
-               pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
-                                         FDI_DP_PORT_WIDTH_SHIFT) + 1;
-
-               ilk_get_fdi_m_n_config(crtc, pipe_config);
-       }
-}
-
 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
                                struct intel_crtc_state *pipe_config)
 {
@@ -4560,8 +4521,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
                /* we cannot read out most state, so don't bother.. */
                pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
        } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
-           DISPLAY_VER(dev_priv) >= 11) {
-               hsw_get_ddi_port_state(crtc, pipe_config);
+                  DISPLAY_VER(dev_priv) >= 11) {
                intel_get_transcoder_timings(crtc, pipe_config);
        }
 

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 93c84f2174b56b2ec7db074249300d309251550f..5bc8d891317853dcd714ca43bf99a49c8c910d01 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -584,6 +584,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
                      struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
                      enum link_m_n_set m_n);
+void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
+                           struct intel_crtc_state *pipe_config);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 
 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 22dbd94cc5fd5eaa1c6b1b17b15b2daa4f394005..b4c6557ba8b93e8b3d1073c848a510e0f4d52ad6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -366,3 +366,21 @@ void lpt_pch_enable(struct intel_atomic_state *state,
 
        lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
 }
+
+void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       u32 tmp;
+
+       if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
+               return;
+
+       crtc_state->has_pch_encoder = true;
+
+       tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
+       crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
+                                FDI_DP_PORT_WIDTH_SHIFT) + 1;
+
+       ilk_get_fdi_m_n_config(crtc, crtc_state);
+}

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index 7f9df2c13cf3dee90558dfd81a1570ab899ec7c0..e0ff331c0bc6d6c4c8b969d5c391c3e6b3f43c09 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -18,5 +18,6 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
 void lpt_pch_enable(struct intel_atomic_state *state,
                    struct intel_crtc *crtc);
+void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
 
 #endif

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e221fbe37fd5ee3bf4ac9d78e2ccd70969965ab..d9f7a729333fa0efed5a49a6ae81a9887f7e5cac 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10212,8 +10212,6 @@ enum skl_power_gate {
 #define  TGL_TRANS_DDI_PORT_MASK       (0xf << TGL_TRANS_DDI_PORT_SHIFT)
 #define  TRANS_DDI_SELECT_PORT(x)      ((x) << TRANS_DDI_PORT_SHIFT)
 #define  TGL_TRANS_DDI_SELECT_PORT(x)  (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
-#define  TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)    (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
-#define  TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
 #define  TRANS_DDI_MODE_SELECT_MASK    (7 << 24)
 #define  TRANS_DDI_MODE_SELECT_HDMI    (0 << 24)
 #define  TRANS_DDI_MODE_SELECT_DVI     (1 << 24)