drm/amdgpu: Use correct gfx deferred error count

In the case of parsing GFX deferred error from SMU corrected error
channel, the error count should be set to 1 instead of parsing from
MISC0 register, which is 0.

Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 736398b0d16d9200861774d4c25c2444bd492fa2..3caac4a1564aa6a7d9b36c78c055130a9b08e33a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -872,9 +872,10 @@ static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle,
                break;
        case ACA_SMU_TYPE_CE:
                bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank);
-               ret = aca_error_cache_log_bank_error(handle, &info,
-                                                    bank->aca_err_type,
-                                                    ACA_REG__MISC0__ERRCNT(misc0));
+               ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
+                       (bank->aca_err_type == ACA_ERROR_TYPE_CE) ?
+                               ACA_REG__MISC0__ERRCNT(misc0) :
+                               1);
                break;
        default:
                return -EINVAL;