int (*prog)(struct nvkm_ram *);
        void (*tidy)(struct nvkm_ram *);
 };
+
+extern const u8 gf100_pte_storage_type_map[256];
 #endif
 
 extern int nouveau_tv_disable;
 extern int nouveau_ignorelid;
 extern int nouveau_duallink;
+extern int nouveau_hdmimhz;
 
 #endif /* __NOUVEAU_CONNECTOR_H__ */
 
        DRM_DEBUG_DRIVER("... modeset      : %d\n", nouveau_modeset);
        DRM_DEBUG_DRIVER("... runpm        : %d\n", nouveau_runtime_pm);
        DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
+       DRM_DEBUG_DRIVER("... hdmimhz      : %d\n", nouveau_hdmimhz);
 }
 
 static const struct dev_pm_ops nouveau_pm_ops = {
 
        }
 }
 
-const struct nvif_driver *
+static const struct nvif_driver *
 nvif_drivers[] = {
 #ifdef __KERNEL__
        &nvif_driver_nvkm,
 
-uint32_t gf100_ce_data[] = {
+static uint32_t gf100_ce_data[] = {
 /* 0x0000: ctx_object */
        0x00000000,
 /* 0x0004: ctx_query_address_high */
        0x00000800,
 };
 
-uint32_t gf100_ce_code[] = {
+static uint32_t gf100_ce_code[] = {
 /* 0x0000: main */
        0x04fe04bd,
        0x3517f000,
 
-uint32_t gt215_ce_data[] = {
+static uint32_t gt215_ce_data[] = {
 /* 0x0000: ctx_object */
        0x00000000,
 /* 0x0004: ctx_dma */
        0x00000800,
 };
 
-uint32_t gt215_ce_code[] = {
+static uint32_t gt215_ce_code[] = {
 /* 0x0000: main */
        0x04fe04bd,
        0x3517f000,
 
 
 #include <nvif/class.h>
 
-const struct nv50_disp_mthd_list
+static const struct nv50_disp_mthd_list
 g94_disp_core_mthd_sor = {
        .mthd = 0x0040,
        .addr = 0x000008,
        .prev = 0x000004,
        .data = {
                { "Global", 1, &nv50_disp_core_mthd_base },
-               {    "DAC", 3, &g84_disp_core_mthd_dac  },
-               {    "SOR", 4, &g94_disp_core_mthd_sor  },
+               {    "DAC", 3, &g84_disp_core_mthd_dac },
+               {    "SOR", 4, &g94_disp_core_mthd_sor },
                {   "PIOR", 3, &nv50_disp_core_mthd_pior },
                {   "HEAD", 2, &g84_disp_core_mthd_head },
                {}
 
        return 0;
 }
 
-const struct nv50_disp_dmac_func
+static const struct nv50_disp_dmac_func
 gp104_disp_core_func = {
        .init = gp104_disp_core_init,
        .fini = gf119_disp_core_fini,
 
-uint32_t gf100_grgpc_data[] = {
+static uint32_t gf100_grgpc_data[] = {
 /* 0x0000: gpc_mmio_list_head */
        0x00000064,
 /* 0x0004: gpc_mmio_list_tail */
        0x00000000,
 };
 
-uint32_t gf100_grgpc_code[] = {
+static uint32_t gf100_grgpc_code[] = {
        0x03a10ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gf117_grgpc_data[] = {
+static uint32_t gf117_grgpc_data[] = {
 /* 0x0000: gpc_mmio_list_head */
        0x0000006c,
 /* 0x0004: gpc_mmio_list_tail */
        0x00000000,
 };
 
-uint32_t gf117_grgpc_code[] = {
+static uint32_t gf117_grgpc_code[] = {
        0x03a10ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gk104_grgpc_data[] = {
+static uint32_t gk104_grgpc_data[] = {
 /* 0x0000: gpc_mmio_list_head */
        0x0000006c,
 /* 0x0004: gpc_mmio_list_tail */
        0x00000000,
 };
 
-uint32_t gk104_grgpc_code[] = {
+static uint32_t gk104_grgpc_code[] = {
        0x03a10ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gk110_grgpc_data[] = {
+static uint32_t gk110_grgpc_data[] = {
 /* 0x0000: gpc_mmio_list_head */
        0x0000006c,
 /* 0x0004: gpc_mmio_list_tail */
        0x00000000,
 };
 
-uint32_t gk110_grgpc_code[] = {
+static uint32_t gk110_grgpc_code[] = {
        0x03a10ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gk208_grgpc_data[] = {
+static uint32_t gk208_grgpc_data[] = {
 /* 0x0000: gpc_mmio_list_head */
        0x0000006c,
 /* 0x0004: gpc_mmio_list_tail */
        0x00000000,
 };
 
-uint32_t gk208_grgpc_code[] = {
+static uint32_t gk208_grgpc_code[] = {
        0x03140ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gm107_grgpc_data[] = {
+static uint32_t gm107_grgpc_data[] = {
 /* 0x0000: gpc_mmio_list_head */
        0x0000006c,
 /* 0x0004: gpc_mmio_list_tail */
        0x00000000,
 };
 
-uint32_t gm107_grgpc_code[] = {
+static uint32_t gm107_grgpc_code[] = {
        0x03410ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gf100_grhub_data[] = {
+static uint32_t gf100_grhub_data[] = {
 /* 0x0000: hub_mmio_list_head */
        0x00000300,
 /* 0x0004: hub_mmio_list_tail */
        0x0417e91c,
 };
 
-uint32_t gf100_grhub_code[] = {
+static uint32_t gf100_grhub_code[] = {
        0x039b0ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gf117_grhub_data[] = {
+static uint32_t gf117_grhub_data[] = {
 /* 0x0000: hub_mmio_list_head */
        0x00000300,
 /* 0x0004: hub_mmio_list_tail */
        0x0417e91c,
 };
 
-uint32_t gf117_grhub_code[] = {
+static uint32_t gf117_grhub_code[] = {
        0x039b0ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gk104_grhub_data[] = {
+static uint32_t gk104_grhub_data[] = {
 /* 0x0000: hub_mmio_list_head */
        0x00000300,
 /* 0x0004: hub_mmio_list_tail */
        0x0417e91c,
 };
 
-uint32_t gk104_grhub_code[] = {
+static uint32_t gk104_grhub_code[] = {
        0x039b0ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gk110_grhub_data[] = {
+static uint32_t gk110_grhub_data[] = {
 /* 0x0000: hub_mmio_list_head */
        0x00000300,
 /* 0x0004: hub_mmio_list_tail */
        0x0417e91c,
 };
 
-uint32_t gk110_grhub_code[] = {
+static uint32_t gk110_grhub_code[] = {
        0x039b0ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gk208_grhub_data[] = {
+static uint32_t gk208_grhub_data[] = {
 /* 0x0000: hub_mmio_list_head */
        0x00000300,
 /* 0x0004: hub_mmio_list_tail */
        0x0417e91c,
 };
 
-uint32_t gk208_grhub_code[] = {
+static uint32_t gk208_grhub_code[] = {
        0x030e0ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
-uint32_t gm107_grhub_data[] = {
+static uint32_t gm107_grhub_data[] = {
 /* 0x0000: hub_mmio_list_head */
        0x00000300,
 /* 0x0004: hub_mmio_list_tail */
        0x0417e91c,
 };
 
-uint32_t gm107_grhub_code[] = {
+static uint32_t gm107_grhub_code[] = {
        0x030e0ef5,
 /* 0x0004: queue_put */
        0x9800d898,
 
 
 #include "fuc/hubgf117.fuc3.h"
 
-struct gf100_gr_ucode
+static struct gf100_gr_ucode
 gf117_gr_fecs_ucode = {
        .code.data = gf117_grhub_code,
        .code.size = sizeof(gf117_grhub_code),
 
 #include "fuc/gpcgf117.fuc3.h"
 
-struct gf100_gr_ucode
+static struct gf100_gr_ucode
 gf117_gr_gpccs_ucode = {
        .code.data = gf117_grgpc_code,
        .code.size = sizeof(gf117_grgpc_code),
 
        {}
 };
 
-const struct nvkm_specdom
+static const struct nvkm_specdom
 gf100_pm_part[] = {
        { 0xe0, (const struct nvkm_specsig[]) {
                        { 0x0f, "part00_pbfb_00", gf100_pbfb_sources },
 
-uint32_t g98_sec_data[] = {
+static uint32_t g98_sec_data[] = {
 /* 0x0000: ctx_dma */
 /* 0x0000: ctx_dma_query */
        0x00000000,
        0x00000000,
 };
 
-uint32_t g98_sec_code[] = {
+static uint32_t g98_sec_code[] = {
        0x17f004bd,
        0x0010fe35,
        0xf10004fe,
 
        ram_exec(&ram->fuc, false);
 }
 
-extern const u8 gf100_pte_storage_type_map[256];
-
 void
 gf100_ram_put(struct nvkm_ram *ram, struct nvkm_mem **pmem)
 {
 
        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 }
 
-const struct i2c_algorithm
+static const struct i2c_algorithm
 nvkm_i2c_aux_i2c_algo = {
        .master_xfer = nvkm_i2c_aux_i2c_xfer,
        .functionality = nvkm_i2c_aux_i2c_func
 
        return 0;
 }
 
-struct nvkm_subdev_func iccsense_func = {
+static const struct nvkm_subdev_func
+iccsense_func = {
        .oneinit = nvkm_iccsense_oneinit,
        .init = nvkm_iccsense_init,
        .dtor = nvkm_iccsense_dtor,
 
        return iobj;
 }
 
-const struct nvkm_memory_func
+static const struct nvkm_memory_func
 nvkm_instobj_func = {
        .dtor = nvkm_instobj_dtor,
        .target = nvkm_instobj_target,
        return nvkm_wo32(iobj->parent, offset, data);
 }
 
-const struct nvkm_memory_func
+static const struct nvkm_memory_func
 nvkm_instobj_func_slow = {
        .dtor = nvkm_instobj_dtor,
        .target = nvkm_instobj_target,
 
        {}
 };
 
-const struct nvkm_mc_map
+static const struct nvkm_mc_map
 g84_mc_intr[] = {
        { 0x04000000, NVKM_ENGINE_DISP },
        { 0x00020000, NVKM_ENGINE_VP },
 
-uint32_t gf100_pmu_data[] = {
+static uint32_t gf100_pmu_data[] = {
 /* 0x0000: proc_kern */
        0x52544e49,
        0x00000000,
        0x00000000,
 };
 
-uint32_t gf100_pmu_code[] = {
+static uint32_t gf100_pmu_code[] = {
        0x03920ef5,
 /* 0x0004: rd32 */
        0x07a007f1,
 
-uint32_t gf119_pmu_data[] = {
+static uint32_t gf119_pmu_data[] = {
 /* 0x0000: proc_kern */
        0x52544e49,
        0x00000000,
        0x00000000,
 };
 
-uint32_t gf119_pmu_code[] = {
+static uint32_t gf119_pmu_code[] = {
        0x03410ef5,
 /* 0x0004: rd32 */
        0x07a007f1,
 
-uint32_t gk208_pmu_data[] = {
+static uint32_t gk208_pmu_data[] = {
 /* 0x0000: proc_kern */
        0x52544e49,
        0x00000000,
        0x00000000,
 };
 
-uint32_t gk208_pmu_code[] = {
+static uint32_t gk208_pmu_code[] = {
        0x02f90ef5,
 /* 0x0004: rd32 */
        0xf607a040,
 
-uint32_t gt215_pmu_data[] = {
+static uint32_t gt215_pmu_data[] = {
 /* 0x0000: proc_kern */
        0x52544e49,
        0x00000000,
        0x00000000,
 };
 
-uint32_t gt215_pmu_code[] = {
+static uint32_t gt215_pmu_code[] = {
        0x03920ef5,
 /* 0x0004: rd32 */
        0x07a007f1,
 
 
 #include <core/tegra.h>
 
-const struct cvb_coef gm20b_cvb_coef[] = {
+static const struct cvb_coef gm20b_cvb_coef[] = {
        /* KHz,             c0,      c1,   c2 */
        /*  76800 */ { 1786666,  -85625, 1632 },
        /* 153600 */ { 1846729,  -87525, 1632 },
        /* 998400 */ { 1316991, 8144, -940, 808, -21583, 226 },
 };
 
-const u32 speedo_to_vmin[] = {
+static const u32 speedo_to_vmin[] = {
        /*   0,      1,      2,      3,      4, */
        950000, 840000, 818750, 840000, 810000,
 };