clk: qcom: gcc-sc7280: Update force mem core bit for UFS ICE clock

Update the force mem core bit for UFS ICE clock to force the core on signal
to remain active during halt state of the clk. When retention bit of the
clock is set the memories of the subsystem will retain the logic across
power states.

Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240531095142.9688-3-quic_tdas@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index c622cd9a9d246ba2934edc204231dc5287cd7a21..b937d513b8148d9bc28247ac9d7656de459442cf 100644 (file)
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -3473,6 +3473,9 @@ static int gcc_sc7280_probe(struct platform_device *pdev)
        qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */
        regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));
 
+       /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
+       qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+
        ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
                        ARRAY_SIZE(gcc_dfs_clocks));
        if (ret)