intel_de_write(dev_priv, CDCLK_CTL, val);
 
        if (pipe != INVALID_PIPE)
-               intel_wait_for_vblank(dev_priv, pipe);
+               intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
 
        if (DISPLAY_VER(dev_priv) >= 11) {
                ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 
                intel_uncore_posting_read(uncore, pipeconf_reg);
                /* Wait for next Vblank to substitue
                 * border color for Color info */
-               intel_wait_for_vblank(dev_priv, pipe);
+               intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
                st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
                status = ((st00 & (1 << 4)) != 0) ?
                        connector_status_connected :
 
         * to change the workaround. */
        hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
        if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
-               intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
-               intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
+               struct intel_crtc *wa_crtc;
+
+               wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
+
+               intel_crtc_wait_for_next_vblank(wa_crtc);
+               intel_crtc_wait_for_next_vblank(wa_crtc);
        }
 }
 
 
        drm_crtc_wait_one_vblank(&crtc->base);
 }
 
-static inline void
-intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
-{
-       struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
-
-       intel_crtc_wait_for_next_vblank(crtc);
-}
-
 static inline void
 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
 {