{
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        int r;
-       uint32_t tmp;
 
        amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
        amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
                amdgpu_mes_kiq_hw_fini(adev);
        }
 
-       if (amdgpu_sriov_vf(adev)) {
-               gfx_v11_0_cp_gfx_enable(adev, false);
-               /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
-               tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
-               tmp &= 0xffffff00;
-               WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
-
+       if (amdgpu_sriov_vf(adev))
+               /* Remove the steps disabling CPG and clearing KIQ position,
+                * so that CP could perform IDLE-SAVE during switch. Those
+                * steps are necessary to avoid a DMAR error in gfx9 but it is
+                * not reproduced on gfx11.
+                */
                return 0;
-       }
+
        gfx_v11_0_cp_enable(adev, false);
        gfx_v11_0_enable_gui_idle_interrupt(adev, false);
 
 
        if (adev->mes.ring.sched.ready)
                mes_v11_0_kiq_dequeue_sched(adev);
 
-       mes_v11_0_enable(adev, false);
+       if (!amdgpu_sriov_vf(adev))
+               mes_v11_0_enable(adev, false);
+
        return 0;
 }