clock-frequency = <0>;
        };
 
+       pmu_a53 {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
        scif_clk: scif {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                        resets = <&cpg 408>;
                };
 
-               timer {
-                       compatible = "arm,armv8-timer";
-                       interrupts = <GIC_PPI 13
-                                       (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 14
-                                       (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 11
-                                       (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 10
-                                       (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
-               };
-
                rwdt: watchdog@e6020000 {
                        compatible = "renesas,r8a77995-wdt",
                                     "renesas,rcar-gen3-wdt";
                        status = "disabled";
                };
 
-               pmu_a53 {
-                       compatible = "arm,cortex-a53-pmu";
-                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-               };
-
                ipmmu_vi0: mmu@febd0000 {
                        compatible = "renesas,ipmmu-r8a77995";
                        reg = <0 0xfebd0000 0 0x1000>;
                        status = "disabled";
                };
        };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+       };
 };