Used sparse(make C=1) to find these loose ends.
v2:
removed unwanted extra line
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 #define mmMM_DATA              0x1
 #define HW_ID_MAX              300
 
-const char *hw_id_names[HW_ID_MAX] = {
+static const char *hw_id_names[HW_ID_MAX] = {
        [MP1_HWID]              = "MP1",
        [MP2_HWID]              = "MP2",
        [THM_HWID]              = "THM",
 
 #define I2C_PRODUCT_INFO_ADDR_SIZE     0x2
 #define I2C_PRODUCT_INFO_OFFSET                0xC0
 
-bool is_fru_eeprom_supported(struct amdgpu_device *adev)
+static bool is_fru_eeprom_supported(struct amdgpu_device *adev)
 {
        /* TODO: Gaming SKUs don't have the FRU EEPROM.
         * Use this hack to address hangs on modprobe on gaming SKUs
        return false;
 }
 
-int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,
+static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,
                           unsigned char *buff)
 {
        int ret, size;
 
        cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
 }
 
-int psp_ta_invoke(struct psp_context *psp,
+static int psp_ta_invoke(struct psp_context *psp,
                  uint32_t ta_cmd_id,
                  uint32_t session_id)
 {
 
                amdgpu_ras_get_context(adev)->error_query_ready = ready;
 }
 
-bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
+static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 {
        if (adev && amdgpu_ras_get_context(adev))
                return amdgpu_ras_get_context(adev)->error_query_ready;
 }
 /* obj end */
 
-void amdgpu_ras_parse_status_code(struct amdgpu_device* adev,
+static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
                                  const char*           invoke_type,
                                  const char*           block_name,
                                  enum ta_ras_status    ret)
 }
 
 /* Trigger XGMI/WAFL error */
-int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
+static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
                                 struct ta_ras_trigger_error_input *block_info)
 {
        int ret;
 
 #endif
 }
 
-int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
+static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
                                struct ttm_buffer_object *tbo,
                                uint64_t flags)
 {
 
        }
 }
 
-bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
+static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
 {
        return amdgpu_sriov_is_debug(adev) ? true : false;
 }
 
-bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
+static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
 {
        return amdgpu_sriov_is_normal(adev) ? true : false;
 }
 
        mqd->cp_hqd_active = 1;
 }
 
-int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
+static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
 {
        uint32_t tmp;
        uint32_t mqd_reg;
        cu_info->lds_size = 64;
 }
 
-const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
+static const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
 {
        .type = AMD_IP_BLOCK_TYPE_GFX,
        .major = 7,
 
        return 0;
 }
 
-int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
+static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
                        struct vi_mqd *mqd)
 {
        uint32_t mqd_reg;
 
        mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 };
 
-void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
+static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
 {
        static void *scratch_reg0;
        static void *scratch_reg1;