drm/amdgpu: Update setting EEPROM table version

Use helper function instead of umc callback to set
EEPROM table version.

Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index b12808c0c331f252a8fabc034f7f2919a7a12b4d..06a62a8a992e9b647a4e88087192f7f5ddc58da3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -404,6 +404,22 @@ static int amdgpu_ras_eeprom_correct_header_tag(
        return res;
 }
 
+static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control)
+{
+       struct amdgpu_device *adev = to_amdgpu_device(control);
+       struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
+
+       switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
+       case IP_VERSION(8, 10, 0):
+       case IP_VERSION(12, 0, 0):
+               hdr->version = RAS_TABLE_VER_V2_1;
+               return;
+       default:
+               hdr->version = RAS_TABLE_VER_V1;
+               return;
+       }
+}
+
 /**
  * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
  * @control: pointer to control structure
@@ -423,11 +439,7 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
        mutex_lock(&control->ras_tbl_mutex);
 
        hdr->header = RAS_TABLE_HDR_VAL;
-       if (adev->umc.ras &&
-           adev->umc.ras->set_eeprom_table_version)
-               adev->umc.ras->set_eeprom_table_version(hdr);
-       else
-               hdr->version = RAS_TABLE_VER_V1;
+       amdgpu_ras_set_eeprom_table_version(control);
 
        if (hdr->version == RAS_TABLE_VER_V2_1) {
                hdr->first_rec_offset = RAS_RECORD_START_V2_1;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index 26d2ae498daf22bf2833cfdde9333c5f26523b44..5954e839d5808dcd4de710355149c3763a68a825 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -66,8 +66,6 @@ struct amdgpu_umc_ras {
                                        void *ras_error_status);
        bool (*check_ecc_err_status)(struct amdgpu_device *adev,
                        enum amdgpu_mca_error_type type, void *ras_error_status);
-       /* support different eeprom table version for different asic */
-       void (*set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header *hdr);
 };
 
 struct amdgpu_umc_funcs {

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
index c4c77257710c973113b4465c27213fb00343289c..a32f87992f2058e46dd278a9646478512ec8e044 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
@@ -442,11 +442,6 @@ static void umc_v8_10_ecc_info_query_ras_error_address(struct amdgpu_device *ade
                umc_v8_10_ecc_info_query_error_address, ras_error_status);
 }
 
-static void umc_v8_10_set_eeprom_table_version(struct amdgpu_ras_eeprom_table_header *hdr)
-{
-       hdr->version = RAS_TABLE_VER_V2_1;
-}
-
 const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {
        .query_ras_error_count = umc_v8_10_query_ras_error_count,
        .query_ras_error_address = umc_v8_10_query_ras_error_address,
@@ -460,5 +455,4 @@ struct amdgpu_umc_ras umc_v8_10_ras = {
        .query_ras_poison_mode = umc_v8_10_query_ras_poison_mode,
        .ecc_info_query_ras_error_count = umc_v8_10_ecc_info_query_ras_error_count,
        .ecc_info_query_ras_error_address = umc_v8_10_ecc_info_query_ras_error_address,
-       .set_eeprom_table_version = umc_v8_10_set_eeprom_table_version,
 };