ARM: dts: rockchip: add saradc nodes

Add the core device nodes for the SARADC found on both the Cortex-A9 series
(rk3066 and rk3188) as well as the newer rk3288.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 7342b2453d6f2c7ed59b0d85c2447a1ff40048c2..9eda0973795f8805f817f44eb23d21bdd3752141 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -98,6 +98,16 @@
                status = "disabled";
        };
 
+       saradc: saradc@ff100000 {
+               compatible = "rockchip,saradc";
+               reg = <0xff100000 0x100>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               #io-channel-cells = <1>;
+               clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+               clock-names = "saradc", "apb_pclk";
+               status = "disabled";
+       };
+
        i2c1: i2c@ff140000 {
                compatible = "rockchip,rk3288-i2c";
                reg = <0xff140000 0x1000>;

diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 8caf85d839019ab1ed47690cf9bb4597de71b2f2..cce4a07d6e04e45fb6f572225cb71d8fbd1131ce 100644 (file)
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -264,4 +264,14 @@
                clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
                status = "disabled";
        };
+
+       saradc: saradc@2006c000 {
+               compatible = "rockchip,saradc";
+               reg = <0x2006c000 0x100>;
+               interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+               #io-channel-cells = <1>;
+               clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+               clock-names = "saradc", "apb_pclk";
+               status = "disabled";
+       };
 };