{
        int ret;
 
-       clk_prepare_lock();
+       lockdep_assert_held(&prepare_lock);
+       if (!core->ops->get_phase)
+               return 0;
+
        /* Always try to update cached phase if possible */
-       if (core->ops->get_phase)
-               core->phase = core->ops->get_phase(core->hw);
-       ret = core->phase;
-       clk_prepare_unlock();
+       ret = core->ops->get_phase(core->hw);
+       if (ret >= 0)
+               core->phase = ret;
 
        return ret;
 }
  */
 int clk_get_phase(struct clk *clk)
 {
+       int ret;
+
        if (!clk)
                return 0;
 
-       return clk_core_get_phase(clk->core);
+       clk_prepare_lock();
+       ret = clk_core_get_phase(clk->core);
+       clk_prepare_unlock();
+
+       return ret;
 }
 EXPORT_SYMBOL_GPL(clk_get_phase);
 
 static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
                                 int level)
 {
-       seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n",
+       int phase;
+
+       seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu ",
                   level * 3 + 1, "",
                   30 - level * 3, c->name,
                   c->enable_count, c->prepare_count, c->protect_count,
-                  clk_core_get_rate(c), clk_core_get_accuracy(c),
-                  clk_core_get_phase(c),
-                  clk_core_get_scaled_duty_cycle(c, 100000));
+                  clk_core_get_rate(c), clk_core_get_accuracy(c));
+
+       phase = clk_core_get_phase(c);
+       if (phase >= 0)
+               seq_printf(s, "%5d", phase);
+       else
+               seq_puts(s, "-----");
+
+       seq_printf(s, " %6d\n", clk_core_get_scaled_duty_cycle(c, 100000));
 }
 
 static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
 
 static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
 {
+       int phase;
        unsigned long min_rate, max_rate;
 
        clk_core_get_boundaries(c, &min_rate, &max_rate);
        seq_printf(s, "\"min_rate\": %lu,", min_rate);
        seq_printf(s, "\"max_rate\": %lu,", max_rate);
        seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
-       seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c));
+       phase = clk_core_get_phase(c);
+       if (phase >= 0)
+               seq_printf(s, "\"phase\": %d,", phase);
        seq_printf(s, "\"duty_cycle\": %u",
                   clk_core_get_scaled_duty_cycle(c, 100000));
 }
                core->accuracy = 0;
 
        /*
-        * Set clk's phase.
+        * Set clk's phase by clk_core_get_phase() caching the phase.
         * Since a phase is by definition relative to its parent, just
         * query the current clock phase, or just assume it's in phase.
         */
-       if (core->ops->get_phase)
-               core->phase = core->ops->get_phase(core->hw);
-       else
-               core->phase = 0;
+       clk_core_get_phase(core);
 
        /*
         * Set clk's duty cycle.