Until this patch, the number of UPs was hard coded for eight.
Replace this with a variable in struct "mlx4_en_port_profile".
Currently, the variable will hold the maximum number of UP,
as before.
The patch creates an infrastructure to add an option for dynamic
change of the actual number of TCs.
Signed-off-by: Inbar Karmy <inbark@mellanox.com>
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Cc: Tarick Bedeir <tarick@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
        int has_ets_tc = 0;
 
        for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
-               if (ets->prio_tc[i] >= MLX4_EN_NUM_UP) {
+               if (ets->prio_tc[i] >= priv->prof->num_up) {
                        en_err(priv, "Bad priority in UP <=> TC mapping. TC: %d, UP: %d\n",
                                        i, ets->prio_tc[i]);
                        return -EINVAL;
 
        channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
 
        channel->rx_count = priv->rx_ring_num;
-       channel->tx_count = priv->tx_ring_num[TX] / MLX4_EN_NUM_UP;
+       channel->tx_count = priv->tx_ring_num[TX] /
+                           priv->prof->num_up;
 }
 
 static int mlx4_en_set_channels(struct net_device *dev,
 
        mutex_lock(&mdev->state_lock);
        xdp_count = priv->tx_ring_num[TX_XDP] ? channel->rx_count : 0;
-       if (channel->tx_count * MLX4_EN_NUM_UP + xdp_count > MAX_TX_RINGS) {
+       if (channel->tx_count * priv->prof->num_up + xdp_count >
+           MAX_TX_RINGS) {
                err = -EINVAL;
                en_err(priv,
                       "Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n",
-                      channel->tx_count * MLX4_EN_NUM_UP + xdp_count,
+                      channel->tx_count * priv->prof->num_up  + xdp_count,
                       MAX_TX_RINGS);
                goto out;
        }
 
        memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
        new_prof.num_tx_rings_p_up = channel->tx_count;
-       new_prof.tx_ring_num[TX] = channel->tx_count * MLX4_EN_NUM_UP;
+       new_prof.tx_ring_num[TX] = channel->tx_count * priv->prof->num_up;
        new_prof.tx_ring_num[TX_XDP] = xdp_count;
        new_prof.rx_ring_num = channel->rx_count;
 
        netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
 
        if (netdev_get_num_tc(dev))
-               mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
+               mlx4_en_setup_tc(dev, priv->prof->num_up);
 
        en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num[TX]);
        en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
 
                params->prof[i].tx_ppp = pfctx;
                params->prof[i].tx_ring_size = MLX4_EN_DEF_TX_RING_SIZE;
                params->prof[i].rx_ring_size = MLX4_EN_DEF_RX_RING_SIZE;
+               params->prof[i].num_up = MLX4_EN_NUM_UP_HIGH;
                params->prof[i].tx_ring_num[TX] = params->num_tx_rings_p_up *
-                       MLX4_EN_NUM_UP;
+                       params->prof[i].num_up;
                params->prof[i].rss_rings = 0;
                params->prof[i].inline_thold = inline_thold;
        }
 
        int i;
        unsigned int offset = 0;
 
-       if (up && up != MLX4_EN_NUM_UP)
+       if (up && up != MLX4_EN_NUM_UP_HIGH)
                return -EINVAL;
 
        netdev_set_num_tc(dev, up);
        if (priv->tx_ring_num[TX] + xdp_ring_num > MAX_TX_RINGS) {
                tx_changed = 1;
                new_prof.tx_ring_num[TX] =
-                       MAX_TX_RINGS - ALIGN(xdp_ring_num, MLX4_EN_NUM_UP);
+                       MAX_TX_RINGS - ALIGN(xdp_ring_num, priv->prof->num_up);
                en_warn(priv, "Reducing the number of TX rings, to not exceed the max total rings number.\n");
        }
 
                priv->flags |= MLX4_EN_DCB_ENABLED;
                priv->cee_config.pfc_state = false;
 
-               for (i = 0; i < MLX4_EN_NUM_UP; i++)
+               for (i = 0; i < MLX4_EN_NUM_UP_HIGH; i++)
                        priv->cee_config.dcb_pfc[i] = pfc_disabled;
 
                if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
 
 #define MLX4_EN_SMALL_PKT_SIZE         64
 #define MLX4_EN_MIN_TX_RING_P_UP       1
 #define MLX4_EN_MAX_TX_RING_P_UP       32
-#define MLX4_EN_NUM_UP                 8
+#define MLX4_EN_NUM_UP_HIGH            8
 #define MLX4_EN_DEF_RX_RING_SIZE       1024
 #define MLX4_EN_DEF_TX_RING_SIZE       MLX4_EN_DEF_RX_RING_SIZE
 #define MAX_TX_RINGS                   (MLX4_EN_MAX_TX_RING_P_UP * \
-                                        MLX4_EN_NUM_UP)
+                                        MLX4_EN_NUM_UP_HIGH)
 
 #define MLX4_EN_DEFAULT_TX_WORK                256
 
        u8 rx_ppp;
        u8 tx_pause;
        u8 tx_ppp;
+       u8 num_up;
        int rss_rings;
        int inline_thold;
        struct hwtstamp_config hwtstamp_config;
 
 struct mlx4_en_cee_config {
        bool    pfc_state;
-       enum    dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP];
+       enum    dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
 };
 #endif