arm64: dts: microchip: add missing cache properties

As all level 2 and level 3 caches are unified, add required
cache-unified and cache-level properties to fix warnings like:

  sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property

Link: https://lore.kernel.org/r/20230421223155.115339-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 0367a00a269b3a2be52a872fdf3f36606e47b427..6f7651b064780bc042ab3ad11454e4c06eb855dc 100644 (file)
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -52,6 +52,8 @@
                };
                L2_0: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
                };
        };