drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCS

Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.

Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
masked register. Re-oops.

A wonder if went through 2 people while having roughly a bug per line...

The problem was introduced in the original patch:

  commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
  Author: Damien Lespiau <damien.lespiau@intel.com>
  Date:   Mon Feb 9 19:33:20 2015 +0000

      drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS

v2: Also fix the register write (Ville)

Reported-by: Robert Beckett <robert.beckett@intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Robert Beckett <robert.beckett@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 558d3dd5a0397b83a24861b4a6b8365e75a1bf79..60ef5406fe5769577164fa43fe5e5489e9946f1d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5718,7 +5718,7 @@ enum skl_disp_power_wells {
 #define HSW_NDE_RSTWRN_OPT     0x46408
 #define  RESET_PCH_HANDSHAKE_ENABLE    (1<<4)
 
-#define FF_SLICE_CS_CHICKEN2                   0x02e4
+#define FF_SLICE_CS_CHICKEN2                   0x20e4
 #define  GEN9_TSG_BARRIER_ACK_DISABLE          (1<<8)
 
 /* GEN7 chicken */

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9e3bfff2d8451e218b643e9d9e045491b194bec9..7006f94b94c15c8e84b061fa7b305df0ebbd97b0 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -88,8 +88,7 @@ static void skl_init_clock_gating(struct drm_device *dev)
 
                /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
                I915_WRITE(FF_SLICE_CS_CHICKEN2,
-                          I915_READ(FF_SLICE_CS_CHICKEN2) |
-                          GEN9_TSG_BARRIER_ACK_DISABLE);
+                          _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
        }
 
        if (INTEL_REVID(dev) <= SKL_REVID_E0)