Modifications for 1.0.5:
======================================================================
+* Fix PUMA download on CCM board
+
* allow 0x... prefix on input
(based on idea by Mads Dydensborg, Tue, 7 Aug 2001)
/*
* Single Write. (Offset 18 in UPM RAM)
*/
- 0x0FFFF804, 0X0FFFF400, 0X3FFFFC47, /* last */
+ 0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
/*
* Exception. (Offset 3c in UPM RAM)
*/
- 0X7FFFFC07, /* last */
+ 0x7FFFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
* Memory controller will be used in 2 modes:
*
* - "read" mode:
- * BR4: 0x10100801 OR4: 0xffff8530
+ * BR4: 0x10100801 OR4: 0xffff8520
* - "load" mode (chip select on UPM B):
- * BR4: 0x101004c1 OR4: 0xffff8630
+ * BR4: 0x101004c1 OR4: 0xffff8600
*
* Default initialization is in "read" mode
*/
#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
-#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
-#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
+#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_2_CLK)
+#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_0_CLK)
#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
BR_PS_8 | BR_MS_UPMB | BR_V)