]> www.infradead.org Git - users/rw/ppcboot.git/commitdiff
Fix PUMA download on CCM board
authorwdenk <wdenk>
Wed, 8 Aug 2001 23:12:32 +0000 (23:12 +0000)
committerwdenk <wdenk>
Wed, 8 Aug 2001 23:12:32 +0000 (23:12 +0000)
CHANGELOG
board/siemens/CCM/ccm.c
include/config_CCM.h

index 7fd546e6a8f8fa25643b40c17a8cd580eaedff7e..cf3c8bff57941c1c3573559da4cf08edde957409 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -56,6 +56,8 @@ To do:
 Modifications for 1.0.5:
 ======================================================================
 
+* Fix PUMA download on CCM board
+
 * allow 0x... prefix on input
   (based on idea by Mads Dydensborg, Tue, 7 Aug 2001)
 
index 631761921b33d7692698072c4e2969f36ed71451..86f4cf384a2fa54aebe38c36e5cc409c7fb0af97 100644 (file)
@@ -117,7 +117,7 @@ const uint puma_table[] =
        /*
         * Single Write. (Offset 18 in UPM RAM)
         */
-       0x0FFFF804, 0X0FFFF400, 0X3FFFFC47, /* last */
+       0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */
                                            _NOT_USED_,
        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
        /*
@@ -136,7 +136,7 @@ const uint puma_table[] =
        /*
         * Exception. (Offset 3c in UPM RAM)
         */
-       0X7FFFFC07, /* last */
+       0x7FFFFC07, /* last */
                    _NOT_USED_, _NOT_USED_, _NOT_USED_,
 };
 
index 1323d8270bba2c72dd828243126595bef8ee0417..ccc2d0b47fa8b63d9f1942baf8dda0fb76d6d890 100644 (file)
  * Memory controller will be used in 2 modes:
  *
  * - "read" mode:
- *     BR4: 0x10100801         OR4: 0xffff8530
+ *     BR4: 0x10100801         OR4: 0xffff8520
  * - "load" mode (chip select on UPM B):
- *     BR4: 0x101004c1         OR4: 0xffff8630
+ *     BR4: 0x101004c1         OR4: 0xffff8600
  *
  * Default initialization is in "read" mode
  */
 #define PUMA_CONF_BASE         0x10100000      /* PUMA Config */
 #define PUMA_CONF_OR_AM                0xFFFF8000      /* 32 kB */
-#define        PUMA_CONF_LOAD_TIMING   (OR_ACS_DIV2     | OR_SCY_3_CLK)
-#define PUMA_CONF_READ_TIMING  (OR_G5LA | OR_BI | OR_SCY_3_CLK)
+#define        PUMA_CONF_LOAD_TIMING   (OR_ACS_DIV2     | OR_SCY_2_CLK)
+#define PUMA_CONF_READ_TIMING  (OR_G5LA | OR_BI | OR_SCY_0_CLK)
 
 #define PUMA_CONF_BR_LOAD      ((PUMA_CONF_BASE & BR_BA_MSK) | \
                                        BR_PS_8  | BR_MS_UPMB | BR_V)