switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
                case VCN_HWID:
                        vcn_harvest_count++;
+                       if (harvest_info->list[i].number_instance == 0)
+                               adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
+                       else
+                               adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
                        break;
                case DMU_HWID:
                        adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 
 static int vcn_v3_0_early_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       int i;
 
        if (amdgpu_sriov_vf(adev)) {
                adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
                adev->vcn.num_enc_rings = 1;
 
        } else {
-               if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
-                       u32 harvest;
-
-                       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-                               harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
-                               if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
-                                       adev->vcn.harvest_config |= 1 << i;
-                       }
-
-                       if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
-                                               AMDGPU_VCN_HARVEST_VCN1))
-                               /* both instances are harvested, disable the block */
-                               return -ENOENT;
-               }
+               if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
+                                                AMDGPU_VCN_HARVEST_VCN1))
+                       /* both instances are harvested, disable the block */
+                       return -ENOENT;
 
                if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
                        adev->vcn.num_enc_rings = 0;