struct temac_local *lp = netdev_priv(ndev);
 
        /* set up unicast MAC address filter set its mac address */
-       mutex_lock(&lp->indirect_mutex);
+       mutex_lock(lp->indirect_mutex);
        temac_indirect_out32(lp, XTE_UAW0_OFFSET,
                             (ndev->dev_addr[0]) |
                             (ndev->dev_addr[1] << 8) |
        temac_indirect_out32(lp, XTE_UAW1_OFFSET,
                             (ndev->dev_addr[4] & 0x000000ff) |
                             (ndev->dev_addr[5] << 8));
-       mutex_unlock(&lp->indirect_mutex);
+       mutex_unlock(lp->indirect_mutex);
 }
 
 static int temac_init_mac_address(struct net_device *ndev, const void *address)
        u32 multi_addr_msw, multi_addr_lsw, val;
        int i;
 
-       mutex_lock(&lp->indirect_mutex);
+       mutex_lock(lp->indirect_mutex);
        if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
            netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
                /*
                temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
                dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
        }
-       mutex_unlock(&lp->indirect_mutex);
+       mutex_unlock(lp->indirect_mutex);
 }
 
 static struct temac_option {
        struct temac_option *tp = &temac_options[0];
        int reg;
 
-       mutex_lock(&lp->indirect_mutex);
+       mutex_lock(lp->indirect_mutex);
        while (tp->opt) {
                reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
                if (options & tp->opt)
                tp++;
        }
        lp->options |= options;
-       mutex_unlock(&lp->indirect_mutex);
+       mutex_unlock(lp->indirect_mutex);
 
        return 0;
 }
 
        dev_dbg(&ndev->dev, "%s()\n", __func__);
 
-       mutex_lock(&lp->indirect_mutex);
+       mutex_lock(lp->indirect_mutex);
        /* Reset the receiver and wait for it to finish reset */
        temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
        timeout = 1000;
        temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
        temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
 
-       mutex_unlock(&lp->indirect_mutex);
+       mutex_unlock(lp->indirect_mutex);
 
        /* Sync default options with HW
         * but leave receiver and transmitter disabled.  */
        /* hash together the state values to decide if something has changed */
        link_state = phy->speed | (phy->duplex << 1) | phy->link;
 
-       mutex_lock(&lp->indirect_mutex);
+       mutex_lock(lp->indirect_mutex);
        if (lp->last_link != link_state) {
                mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
                mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
                lp->last_link = link_state;
                phy_print_status(phy);
        }
-       mutex_unlock(&lp->indirect_mutex);
+       mutex_unlock(lp->indirect_mutex);
 }
 
 #ifdef CONFIG_64BIT
        lp->dev = &pdev->dev;
        lp->options = XTE_OPTION_DEFAULTS;
        spin_lock_init(&lp->rx_lock);
-       mutex_init(&lp->indirect_mutex);
+
+       /* Setup mutex for synchronization of indirect register access */
+       if (pdata) {
+               if (!pdata->indirect_mutex) {
+                       dev_err(&pdev->dev,
+                               "indirect_mutex missing in platform_data\n");
+                       return -EINVAL;
+               }
+               lp->indirect_mutex = pdata->indirect_mutex;
+       } else {
+               lp->indirect_mutex = devm_kmalloc(&pdev->dev,
+                                                 sizeof(*lp->indirect_mutex),
+                                                 GFP_KERNEL);
+               mutex_init(lp->indirect_mutex);
+       }
 
        /* map device registers */
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
        /* Write the PHY address to the MIIM Access Initiator register.
         * When the transfer completes, the PHY register value will appear
         * in the LSW0 register */
-       mutex_lock(&lp->indirect_mutex);
+       mutex_lock(lp->indirect_mutex);
        temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg);
        rc = temac_indirect_in32(lp, XTE_MIIMAI_OFFSET);
-       mutex_unlock(&lp->indirect_mutex);
+       mutex_unlock(lp->indirect_mutex);
 
        dev_dbg(lp->dev, "temac_mdio_read(phy_id=%i, reg=%x) == %x\n",
                phy_id, reg, rc);
        /* First write the desired value into the write data register
         * and then write the address into the access initiator register
         */
-       mutex_lock(&lp->indirect_mutex);
+       mutex_lock(lp->indirect_mutex);
        temac_indirect_out32(lp, XTE_MGTDR_OFFSET, val);
        temac_indirect_out32(lp, XTE_MIIMAI_OFFSET, (phy_id << 5) | reg);
-       mutex_unlock(&lp->indirect_mutex);
+       mutex_unlock(lp->indirect_mutex);
 
        return 0;
 }
 
        /* Enable the MDIO bus by asserting the enable bit and writing
         * in the clock config */
-       mutex_lock(&lp->indirect_mutex);
+       mutex_lock(lp->indirect_mutex);
        temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);
-       mutex_unlock(&lp->indirect_mutex);
+       mutex_unlock(lp->indirect_mutex);
 
        bus = devm_mdiobus_alloc(&pdev->dev);
        if (!bus)
        if (rc)
                return rc;
 
-       mutex_lock(&lp->indirect_mutex);
+       mutex_lock(lp->indirect_mutex);
        dev_dbg(lp->dev, "MDIO bus registered;  MC:%x\n",
                temac_indirect_in32(lp, XTE_MC_OFFSET));
-       mutex_unlock(&lp->indirect_mutex);
+       mutex_unlock(lp->indirect_mutex);
        return 0;
 }