switch (pipe) {
case PIPE_A:
- dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+ dsparb = intel_uncore_read(&dev_priv->uncore,
+ DSPARB(dev_priv));
dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
break;
case PIPE_B:
- dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+ dsparb = intel_uncore_read(&dev_priv->uncore,
+ DSPARB(dev_priv));
dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
- u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+ u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
int size;
size = dsparb & 0x7f;
static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
- u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+ u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
int size;
size = dsparb & 0x1ff;
static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
- u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+ u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
int size;
size = dsparb & 0x7f;
switch (crtc->pipe) {
case PIPE_A:
- dsparb = intel_uncore_read_fw(uncore, DSPARB);
+ dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
- intel_uncore_write_fw(uncore, DSPARB, dsparb);
+ intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
break;
case PIPE_B:
- dsparb = intel_uncore_read_fw(uncore, DSPARB);
+ dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
- intel_uncore_write_fw(uncore, DSPARB, dsparb);
+ intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
break;
case PIPE_C:
break;
}
- intel_uncore_posting_read_fw(uncore, DSPARB);
+ intel_uncore_posting_read_fw(uncore, DSPARB(dev_priv));
spin_unlock(&uncore->lock);
}
/* Display arbitration control */
if (GRAPHICS_VER(dev_priv) <= 4)
- dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
+ dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv,
+ DSPARB(dev_priv));
if (GRAPHICS_VER(dev_priv) == 4)
pci_read_config_word(pdev, GCDGMBUS,
/* Display arbitration */
if (GRAPHICS_VER(dev_priv) <= 4)
- intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
+ intel_de_write(dev_priv, DSPARB(dev_priv),
+ dev_priv->regfile.saveDSPARB);
intel_vga_redisable(dev_priv);