static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
                unsigned long wa_lock_flags;
                raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
-               generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, bit));
+               generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, bit));
                raw_spin_unlock_irqrestore(&bank->wa_lock, wa_lock_flags);
 
 * GENERIC CHAINED GPIO irqchips: these are the same as "CHAINED GPIO irqchips",
 
                return IRQ_NONE;
 
        for_each_set_bit(gpio, &irqs, gc->ngpio)
-               generic_handle_irq(irq_find_mapping(gc->irqdomain, gpio));
+               generic_handle_irq(irq_find_mapping(gc->irq.domain, gpio));
        bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
 
        return IRQ_HANDLED;
 
        unsigned long gpio;
 
        for_each_set_bit(gpio, &irq_mask, 2)
-               generic_handle_irq(irq_find_mapping(chip->irqdomain,
+               generic_handle_irq(irq_find_mapping(chip->irq.domain,
                        19 + gpio*24));
 
        raw_spin_lock(&dio48egpio->lock);
 
                for_each_set_bit(bit_num, &irq_mask, 8) {
                        gpio = bit_num + boundary * 8;
 
-                       generic_handle_irq(irq_find_mapping(chip->irqdomain,
+                       generic_handle_irq(irq_find_mapping(chip->irq.domain,
                                gpio));
                }
        }
 
        int gpio;
 
        for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
-               generic_handle_irq(irq_find_mapping(chip->irqdomain, gpio));
+               generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
 
        raw_spin_lock(&idio16gpio->lock);
 
 
 
                for_each_set_bit(bit, &pending, 8) {
                        unsigned int child_irq;
-                       child_irq = irq_find_mapping(adnp->gpio.irqdomain,
+                       child_irq = irq_find_mapping(adnp->gpio.irq.domain,
                                                     base + bit);
                        handle_nested_irq(child_irq);
                }
 
        altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
        chip = irq_desc_get_chip(desc);
        mm_gc = &altera_gc->mmchip;
-       irqdomain = altera_gc->mmchip.gc.irqdomain;
+       irqdomain = altera_gc->mmchip.gc.irq.domain;
 
        chained_irq_enter(chip, desc);
 
        altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
        chip = irq_desc_get_chip(desc);
        mm_gc = &altera_gc->mmchip;
-       irqdomain = altera_gc->mmchip.gc.irqdomain;
+       irqdomain = altera_gc->mmchip.gc.irq.domain;
 
        chained_irq_enter(chip, desc);
 
 
                reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS));
 
                for_each_set_bit(p, ®, 32) {
-                       girq = irq_find_mapping(gc->irqdomain, i * 32 + p);
+                       girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
                        generic_handle_irq(girq);
                }
 
 
        if (pending) {
                for_each_set_bit(irq, &pending, gc->ngpio)
                        generic_handle_irq(
-                               irq_linear_revmap(gc->irqdomain, irq));
+                               irq_linear_revmap(gc->irq.domain, irq));
        }
 
        chained_irq_exit(irqchip, desc);
 
 
        for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
                if (pending & BIT(gpio)) {
-                       virq = irq_find_mapping(cg->chip.irqdomain, gpio);
+                       virq = irq_find_mapping(cg->chip.irq.domain, gpio);
                        handle_nested_irq(virq);
                }
        }
 
                return;
        }
 
-       irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
+       irq = irq_find_mapping(dln2->gpio.irq.domain, pin);
        if (!irq) {
                dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
                return;
 
        stat = readl(g->base + GPIO_INT_STAT);
        if (stat)
                for_each_set_bit(offset, &stat, gc->ngpio)
-                       generic_handle_irq(irq_find_mapping(gc->irqdomain,
+                       generic_handle_irq(irq_find_mapping(gc->irq.domain,
                                                            offset));
 
        chained_irq_exit(irqchip, desc);
 
                flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
 
        for_each_set_bit(i, &flag, 32)
-               generic_handle_irq(irq_linear_revmap(gc->irqdomain, i));
+               generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
        chained_irq_exit(irq_chip, desc);
 }
 
 
                        mask = BIT(gpio);
                        /* Clear before handling so we can't lose an edge */
                        writel(mask, gedr);
-                       generic_handle_irq(irq_find_mapping(gc->irqdomain,
+                       generic_handle_irq(irq_find_mapping(gc->irq.domain,
                                                            base + gpio));
                }
        }
 
                        mask = BIT(pin);
                        /* Clear before handling so we don't lose an edge */
                        outl(mask, reg);
-                       irq = irq_find_mapping(lg->chip.irqdomain, base + pin);
+                       irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
                        generic_handle_irq(irq);
                }
        }
 
 
        do {
                level = __ffs(pending);
-               handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
+               handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
                                                   level));
 
                pending &= ~(1 << level);
 
                for_each_set_bit(gpio, &pending, 32) {
                        unsigned int irq;
 
-                       irq = irq_find_mapping(gc->irqdomain, base + gpio);
+                       irq = irq_find_mapping(gc->irq.domain, base + gpio);
                        generic_handle_irq(irq);
                }
        }
 
 
                        raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
 
-                       generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
+                       generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
                                                            bit));
 
                        raw_spin_unlock_irqrestore(&bank->wa_lock,
 
        for (i = 0; i < NBANK(chip); i++) {
                while (pending[i]) {
                        level = __ffs(pending[i]);
-                       handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
+                       handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
                                                        level + (BANK_SZ * i)));
                        pending[i] &= ~(1 << level);
                        nhandled++;
 
        mutex_unlock(&gpio->lock);
 
        for_each_set_bit(i, &change, gpio->chip.ngpio)
-               handle_nested_irq(irq_find_mapping(gpio->chip.irqdomain, i));
+               handle_nested_irq(irq_find_mapping(gpio->chip.irq.domain, i));
 
        return IRQ_HANDLED;
 }
 
                return IRQ_NONE;
 
        for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
-               generic_handle_irq(irq_find_mapping(chip->irqdomain, gpio));
+               generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
 
        raw_spin_lock(&idio16gpio->lock);
 
 
        pending = readb(pl061->base + GPIOMIS);
        if (pending) {
                for_each_set_bit(offset, &pending, PL061_GPIO_NR)
-                       generic_handle_irq(irq_find_mapping(gc->irqdomain,
+                       generic_handle_irq(irq_find_mapping(gc->irq.domain,
                                                            offset));
        }
 
 
                          gpio_rcar_read(p, INTMSK))) {
                offset = __ffs(pending);
                gpio_rcar_write(p, INTCLR, BIT(offset));
-               generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
+               generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
                                                    offset));
                irqs_handled++;
        }
 
        struct gpio_reg *r = to_gpio_reg(gc);
        int irq = r->irqs[offset];
 
-       if (irq >= 0 && r->irqdomain)
-               irq = irq_find_mapping(r->irqdomain, irq);
+       if (irq >= 0 && r->irq.domain)
+               irq = irq_find_mapping(r->irq.domain, irq);
 
        return irq;
 }
 
                while (stat) {
                        int bit = __ffs(stat);
                        int line = bank * 8 + bit;
-                       int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
+                       int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
                                                         line);
 
                        handle_nested_irq(child_irq);
 
                while (stat) {
                        int bit = __ffs(stat);
                        int line = i * 8 + bit;
-                       int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
+                       int irq = irq_find_mapping(tc3589x_gpio->chip.irq.domain,
                                                   line);
 
                        handle_nested_irq(irq);
 
        for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
                vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
 
-               generic_handle_irq(irq_find_mapping(port->gc.irqdomain, pin));
+               generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
        }
 
        chained_irq_exit(chip, desc);
 
                        offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
                        mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
                                                                BIT(gpio);
-                       virq = irq_find_mapping(wg->chip.irqdomain, gpio);
+                       virq = irq_find_mapping(wg->chip.irq.domain, gpio);
                        handle_nested_irq(virq);
                        regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
                                                                mask, mask);
 
                        int_id = inb(ws16c48gpio->base + 8 + port);
                        for_each_set_bit(gpio, &int_id, 8)
                                generic_handle_irq(irq_find_mapping(
-                                       chip->irqdomain, gpio + 8*port));
+                                       chip->irq.domain, gpio + 8*port));
                }
 
                int_pending = inb(ws16c48gpio->base + 6) & 0x7;
 
        if (!priv->irq_domain)
                return -ENODEV;
 
-       priv->gc.irqdomain = priv->irq_domain;
+       priv->gc.irq.domain = priv->irq_domain;
 
        ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
        if (ret) {
 
 
                if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
                        generic_handle_irq(irq_find_mapping(
-                                               priv->chip.irqdomain, gpio));
+                                               priv->chip.irq.domain, gpio));
        }
        chained_irq_exit(irqchip, desc);
 }
 
        writew_relaxed(pending, chip->base + ZX_GPIO_IC);
        if (pending) {
                for_each_set_bit(offset, &pending, ZX_GPIO_NR)
-                       generic_handle_irq(irq_find_mapping(gc->irqdomain,
+                       generic_handle_irq(irq_find_mapping(gc->irq.domain,
                                                            offset));
        }
 
 
                                      unsigned long pending)
 {
        unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
-       struct irq_domain *irqdomain = gpio->chip.irqdomain;
+       struct irq_domain *irqdomain = gpio->chip.irq.domain;
        int offset;
 
        if (!pending)
 
 {
        unsigned int offset;
 
-       if (!gpiochip->irqdomain) {
+       if (!gpiochip->irq.domain) {
                chip_err(gpiochip, "called %s before setting up irqchip\n",
                         __func__);
                return;
        for (offset = 0; offset < gpiochip->ngpio; offset++) {
                if (!gpiochip_irqchip_irq_valid(gpiochip, offset))
                        continue;
-               irq_set_parent(irq_find_mapping(gpiochip->irqdomain, offset),
+               irq_set_parent(irq_find_mapping(gpiochip->irq.domain, offset),
                               parent_irq);
        }
 }
 {
        if (!gpiochip_irqchip_irq_valid(chip, offset))
                return -ENXIO;
-       return irq_create_mapping(chip->irqdomain, offset);
+       return irq_create_mapping(chip->irq.domain, offset);
 }
 
 /**
  */
 static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip)
 {
-       unsigned int offset;
+       unsigned int offset, irq;
 
        acpi_gpiochip_free_interrupts(gpiochip);
 
        }
 
        /* Remove all IRQ mappings and delete the domain */
-       if (gpiochip->irqdomain) {
+       if (gpiochip->irq.domain) {
                for (offset = 0; offset < gpiochip->ngpio; offset++) {
                        if (!gpiochip_irqchip_irq_valid(gpiochip, offset))
                                continue;
-                       irq_dispose_mapping(
-                               irq_find_mapping(gpiochip->irqdomain, offset));
+
+                       irq = irq_find_mapping(gpiochip->irq.domain, offset);
+                       irq_dispose_mapping(irq);
                }
-               irq_domain_remove(gpiochip->irqdomain);
+
+               irq_domain_remove(gpiochip->irq.domain);
        }
 
        if (gpiochip->irq.chip) {
        gpiochip->irq_default_type = type;
        gpiochip->to_irq = gpiochip_to_irq;
        gpiochip->lock_key = lock_key;
-       gpiochip->irqdomain = irq_domain_add_simple(of_node,
+       gpiochip->irq.domain = irq_domain_add_simple(of_node,
                                        gpiochip->ngpio, first_irq,
                                        &gpiochip_domain_ops, gpiochip);
-       if (!gpiochip->irqdomain) {
+       if (!gpiochip->irq.domain) {
                gpiochip->irq.chip = NULL;
                return -EINVAL;
        }
 
                /* FIXME: no clue why the code looks up the type here */
                type = pc->irq_type[gpio];
 
-               generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
+               generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.irqdomain,
                                                     gpio));
        }
 }
        enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
        const char *fname = bcm2835_functions[fsel];
        int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
-       int irq = irq_find_mapping(chip->irqdomain, offset);
+       int irq = irq_find_mapping(chip->irq.domain, offset);
 
        seq_printf(s, "function %s in %s; irq %d (%s)",
                fname, value ? "hi" : "lo",
 
 
                for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
                        unsigned pin = NGPIOS_PER_BANK * i + bit;
-                       int child_irq = irq_find_mapping(gc->irqdomain, pin);
+                       int child_irq = irq_find_mapping(gc->irq.domain, pin);
 
                        /*
                         * Clear the interrupt before invoking the
 
                pending = readl(reg);
                raw_spin_unlock(&vg->lock);
                for_each_set_bit(pin, &pending, 32) {
-                       virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
+                       virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
                        generic_handle_irq(virq);
                }
        }
 
                unsigned irq, offset;
 
                offset = pctrl->intr_lines[intr_line];
-               irq = irq_find_mapping(gc->irqdomain, offset);
+               irq = irq_find_mapping(gc->irq.domain, offset);
                generic_handle_irq(irq);
        }
 
 
                        if (padno >= community->npins)
                                break;
 
-                       irq = irq_find_mapping(gc->irqdomain,
+                       irq = irq_find_mapping(gc->irq.domain,
                                               community->pin_base + padno);
                        generic_handle_irq(irq);
 
 
        struct gpio_chip *gc = irq_desc_get_handler_data(desc);
        struct irq_chip *chip = irq_desc_get_chip(desc);
        struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
-       struct irq_domain *d = gc->irqdomain;
+       struct irq_domain *d = gc->irq.domain;
        int i;
 
        chained_irq_enter(chip, desc);
 
        u32 falling = nmk_chip->fimsc & BIT(offset);
        u32 rising = nmk_chip->rimsc & BIT(offset);
        int gpio = nmk_chip->chip.base + offset;
-       int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset);
+       int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
        struct irq_data *d = irq_get_irq_data(irq);
 
        if (!rising && !falling)
        while (status) {
                int bit = __ffs(status);
 
-               generic_handle_irq(irq_find_mapping(chip->irqdomain, bit));
+               generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
                status &= ~BIT(bit);
        }
 
 
                        regval = readl(regs + i);
                        if (!(regval & PIN_IRQ_PENDING))
                                continue;
-                       irq = irq_find_mapping(gc->irqdomain, irqnr + i);
+                       irq = irq_find_mapping(gc->irq.domain, irqnr + i);
                        generic_handle_irq(irq);
                        /* Clear interrupt */
                        writel(regval, regs + i);
 
 
                for_each_set_bit(n, &isr, BITS_PER_LONG) {
                        generic_handle_irq(irq_find_mapping(
-                                          gpio_chip->irqdomain, n));
+                                          gpio_chip->irq.domain, n));
                }
        }
        chained_irq_exit(chip, desc);
 
 
                for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
                        int offset = pinoffset + irqoffset;
-                       int pin_irq = irq_find_mapping(chip->irqdomain, offset);
+                       int pin_irq = irq_find_mapping(chip->irq.domain, offset);
 
                        dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
                                pin_irq, offset);
 
                    ((gpio_bit_changed || intcap_changed) &&
                        (BIT(i) & mcp->irq_fall) && !gpio_set) ||
                    defval_changed) {
-                       child_irq = irq_find_mapping(mcp->chip.irqdomain, i);
+                       child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
                        handle_nested_irq(child_irq);
                }
        }
 
        stat = readl(bank->reg_base + IRQ_PENDING);
 
        for_each_set_bit(pin, &stat, BITS_PER_LONG)
-               generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
+               generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
 
        chained_irq_exit(chip, desc);
 }
 
        pending = pic32_gpio_get_pending(gc, stat);
 
        for_each_set_bit(pin, &pending, BITS_PER_LONG)
-               generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
+               generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
 
        chained_irq_exit(chip, desc);
 }
 
        pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
                gpio_readl(bank, GPIO_INTERRUPT_EN);
        for_each_set_bit(pin, &pending, 16)
-               generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
+               generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
        chained_irq_exit(chip, desc);
 }
 
 
                                        continue;
                        }
 
-                       generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n));
+                       generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n));
                }
        }
 }
 
 
        status = val;
        for_each_set_bit(n, &status, pctl->data->ngpios)
-               handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n));
+               handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
 
        return IRQ_HANDLED;
 }
 
                g = &pctrl->soc->groups[i];
                val = readl(pctrl->regs + g->intr_status_reg);
                if (val & BIT(g->intr_status_bit)) {
-                       irq_pin = irq_find_mapping(gc->irqdomain, i);
+                       irq_pin = irq_find_mapping(gc->irq.domain, i);
                        generic_handle_irq(irq_pin);
                        handled++;
                }
 
                                __func__, gc->label,
                                bank->gpio_offset + pin_in_bank);
                        generic_handle_irq(
-                               irq_find_mapping(gc->irqdomain,
+                               irq_find_mapping(gc->irq.domain,
                                        bank->gpio_offset + pin_in_bank));
                }
 
 
                if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
                        pr_debug("%s: gpio id %d idx %d happens\n",
                                __func__, bank->id, idx);
-                       generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
+                       generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +
                                        bank->id * SIRFSOC_GPIO_BANK_SIZE));
                }
 
 
                        /* get correct irq line number */
                        pin = i * MAX_GPIO_PER_REG + pin;
                        generic_handle_irq(
-                               irq_find_mapping(gc->irqdomain, pin));
+                               irq_find_mapping(gc->irq.domain, pin));
                }
        }
        chained_irq_exit(irqchip, desc);
 
        if (!(gpe_sts_reg & GPE0A_PME_B0_STS_BIT))
                return IRQ_NONE;
 
-       generic_handle_irq(irq_find_mapping(chip->irqdomain,
+       generic_handle_irq(irq_find_mapping(chip->irq.domain,
                                            GPE0A_PME_B0_VIRT_GPIO_PIN));
 
        pm_system_wakeup();
 
         */
        struct irq_chip *chip;
 
+       /**
+        * @domain:
+        *
+        * Interrupt translation domain; responsible for mapping between GPIO
+        * hwirq number and Linux IRQ number.
+        */
+       struct irq_domain *domain;
+
        /**
         * @domain_ops:
         *
  *     safely.
  * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
  *     direction safely.
- * @irqdomain: Interrupt translation domain; responsible for mapping
- *     between GPIO hwirq number and linux irq number
  * @irq_handler: the irq handler to use (often a predefined irq core function)
  *     for GPIO IRQs, provided by GPIO driver
  * @irq_default_type: default IRQ triggering type applied during GPIO driver
         * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
         * to handle IRQs for most practical cases.
         */
-       struct irq_domain       *irqdomain;
        irq_flow_handler_t      irq_handler;
        unsigned int            irq_default_type;
        unsigned int            irq_chained_parent;