CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-       CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
-       CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
+       CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+       CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
        CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
 
        if (cpu_is_omap3517()) {
                cpu_mask = RATE_IN_34XX;
-               cpu_clkflg = CK_3517;
+               cpu_clkflg = CK_AM35XX;
        } else if (cpu_is_omap3630()) {
                cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
                cpu_clkflg = CK_36XX;
 
 #define CK_243X                (1 << 5)        /* 243x, 253x */
 #define CK_3430ES1     (1 << 6)        /* 34xxES1 only */
 #define CK_3430ES2PLUS (1 << 7)        /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_3505                (1 << 8)
-#define CK_3517                (1 << 9)
+#define CK_AM35XX      (1 << 9)        /* Sitara AM35xx */
 #define CK_36XX                (1 << 10)       /* 36xx/37xx-specific clocks */
 #define CK_443X                (1 << 11)
 #define CK_TI816X      (1 << 12)
 
 
 #define CK_34XX                (CK_3430ES1 | CK_3430ES2PLUS)
-#define CK_AM35XX      (CK_3505 | CK_3517)     /* all Sitara AM35xx */
 #define CK_3XXX                (CK_34XX | CK_AM35XX | CK_36XX)