FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
                phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 
-       /* FIME: write the MSB of the phy_addr in CTRL1
-        * iwl_write_direct32(priv,
-               IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
-               ((phy_addr & MSB_MSK)
-                       << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
-        */
        iwl_write_direct32(priv,
-               FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
+               FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
+               (iwl_get_dma_hi_address(phy_addr)
+                       << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
+
        iwl_write_direct32(priv,
                FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
                1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |