drm/panel: s6e63m0: Fix init sequence

The init sequence consist of a number of unknown settings
for the display controller. This patch achieves two things:

- Fix an error that must have happened when the driver was
  converted from the backlight subsystem: the 0xb8
  configuration command was lost and added as a tail to
  the previous command.

- Update some minor settings in some bytes here and there
  according to changes in the Samsung GT-I9070 and
  Samsung GT-S7710 code dumps. Since two other devices use
  these settings they probably reflect trimmings later
  found to be better for the display rather than
  customizations for these devices.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Cc: Stephan Gerhold <stephan@gerhold.net>
Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201117175621.870085-3-linus.walleij@linaro.org

diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c b/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c
index 0418d6f1530b7f68994a615ccf0d42b996158ef9..6b4e97bfd46ee01e3c0b8db6d338663af37ecc7e 100644 (file)
--- a/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c
+++ b/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c
@@ -397,7 +397,7 @@ static void s6e63m0_init(struct s6e63m0 *ctx)
 {
        s6e63m0_dcs_write_seq_static(ctx, MCS_PANELCTL,
                                     0x01, 0x27, 0x27, 0x07, 0x07, 0x54, 0x9f,
-                                    0x63, 0x86, 0x1a, 0x33, 0x0d, 0x00, 0x00);
+                                    0x63, 0x8f, 0x1a, 0x33, 0x0d, 0x00, 0x00);
 
        s6e63m0_dcs_write_seq_static(ctx, MCS_DISCTL,
                                     0x02, 0x03, 0x1c, 0x10, 0x10);
@@ -413,9 +413,8 @@ static void s6e63m0_init(struct s6e63m0 *ctx)
                                     0x01);
 
        s6e63m0_dcs_write_seq_static(ctx, MCS_SRCCTL,
-                                    0x00, 0x8c, 0x07);
-       s6e63m0_dcs_write_seq_static(ctx, 0xb3,
-                                    0xc);
+                                    0x00, 0x8e, 0x07);
+       s6e63m0_dcs_write_seq_static(ctx, 0xb3, 0x6c);
 
        s6e63m0_dcs_write_seq_static(ctx, 0xb5,
                                     0x2c, 0x12, 0x0c, 0x0a, 0x10, 0x0e, 0x17,
@@ -434,9 +433,12 @@ static void s6e63m0_init(struct s6e63m0 *ctx)
                                     0x13, 0x1f, 0x1a, 0x2a, 0x24, 0x1f, 0x1b,
                                     0x1a, 0x17, 0x2b, 0x26, 0x22, 0x20, 0x3a,
                                     0x34, 0x30, 0x2c, 0x29, 0x26, 0x25, 0x23,
-                                    0x21, 0x20, 0x1e, 0x1e, 0x00, 0x00, 0x11,
-                                    0x22, 0x33, 0x44, 0x44, 0x44, 0x55, 0x55,
-                                    0x66, 0x66, 0x66, 0x66, 0x66, 0x66);
+                                    0x21, 0x20, 0x1e, 0x1e);
+
+       s6e63m0_dcs_write_seq_static(ctx, 0xb8,
+                                    0x00, 0x00, 0x11, 0x22, 0x33, 0x44, 0x44,
+                                    0x44, 0x55, 0x55, 0x66, 0x66, 0x66, 0x66,
+                                    0x66, 0x66);
 
        s6e63m0_dcs_write_seq_static(ctx, 0xb9,
                                     0x2c, 0x12, 0x0c, 0x0a, 0x10, 0x0e, 0x17,
@@ -456,7 +458,7 @@ static void s6e63m0_init(struct s6e63m0 *ctx)
                                     0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x06,
                                     0x09, 0x0d, 0x0f, 0x12, 0x15, 0x18);
 
-       s6e63m0_dcs_write_seq_static(ctx, 0xb2,
+       s6e63m0_dcs_write_seq_static(ctx, MCS_TEMP_SWIRE,
                                     0x10, 0x10, 0x0b, 0x05);
 
        s6e63m0_dcs_write_seq_static(ctx, MCS_MIECTL1,