#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
#define X86_FEATURE_IBRS ( 7*32+20) /* Control Speculation Control */
-#define X86_FEATURE_STIPB ( 7*32+21) /* Single Thread Indirect Branch Predictors */
+#define X86_FEATURE_STIBP ( 7*32+21) /* Single Thread Indirect Branch Predictors */
#define X86_FEATURE_IA32_ARCH_CAPS ( 7*32+22) /* Control Speculation Control */
#define X86_FEATURE_IBRS_ATT ( 7*32+23) /* IBRS all the time */
{ X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 },
{ X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 },
{ X86_FEATURE_IBRS, CR_EDX,26, 0x00000007, 0 },
- { X86_FEATURE_STIPB, CR_EDX,27, 0x00000007, 0 },
+ { X86_FEATURE_STIBP, CR_EDX,27, 0x00000007, 0 },
{ X86_FEATURE_IA32_ARCH_CAPS, CR_EDX,29, 0x00000007, 0 },
{ X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a, 0 },
{ X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a, 0 },
/* Aka !ibrs_supported and !ibpb_supported */
if ( !boot_cpu_has(X86_FEATURE_IBRS) )
entry->edx &= !(1u << KVM_CPUID_BIT_IBRS);
- if ( !boot_cpu_has(X86_FEATURE_STIPB) )
+ if ( !boot_cpu_has(X86_FEATURE_STIBP) )
entry->edx &= !(1u << KVM_CPUID_BIT_STIBP);
} else {
entry->ebx = 0;