[Why]
Hardware team remeasured, need to update timings
to increase latency slightly and avoid intermittent
underflows.
[How]
sr exit latency update.
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
                },
        .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
        .num_states = 1,
-       .sr_exit_time_us = 12,
+       .sr_exit_time_us = 15.5,
        .sr_enter_plus_exit_time_us = 20,
        .urgent_latency_us = 4.0,
        .urgent_latency_pixel_data_only_us = 4.0,