#define HAS_DP20(dev_priv)     (IS_DG2(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)       (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
-#define HAS_DDI(dev_priv)               (INTEL_INFO(dev_priv)->display.has_ddi)
+#define HAS_DDI(dev_priv)               (DISPLAY_VER(dev_priv) >= 9 || \
+                                         IS_BROADWELL(dev_priv) || \
+                                         IS_HASWELL(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)               (INTEL_INFO(dev_priv)->display.has_psr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
 
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
        .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
-       .display.has_ddi = 1, \
        .display.has_fpga_dbg = 1, \
        .display.has_dp_mst = 1, \
        .has_rc6p = 0 /* RC6p removed-by HSW */, \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
                BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
        .has_64bit_reloc = 1, \
-       .display.has_ddi = 1, \
        .display.has_fpga_dbg = 1, \
        .display.fbc_mask = BIT(INTEL_FBC_A), \
        .display.has_hdcp = 1, \
        .dbuf.size = 4096,                                                      \
        .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |         \
                BIT(DBUF_S4),                                                   \
-       .display.has_ddi = 1,                                                   \
        .display.has_dmc = 1,                                                   \
        .display.has_dp_mst = 1,                                                \
        .display.has_dsb = 1,                                                   \